Low power, low cost, and high performance factors dictate the design of many microprocessors targeted to the low power computing market. The floating point unit occupies a significant percentage of the silicon area in a microprocessor due its wide data bandwidth (for double precision computations) and the area occupied by the multiply array. For microprocessors designed for portable products, the design site of the floating point unit plays an important role in the low cost factor driven by reduced chip area. Some microprocessors have multiply-add fused floating point units with a reduced multiply array, requiring two passes through the array for operations involving double precision multiplies. The paper discusses the design complexities around the dual pass multiply array and its effect on area and performance. Floating point unit areas and their associated multiply array areas are compared for a single and dual pass implementation in a given technology (PowerPC 604eTM and PowerPC 603eTM microprocessors, respectively).

The PowerPC 603 microprocessor is designed for low power, low cost computing applications. A RAM built-in-self-test (BIST) implementation tests the split 8k instruction and data caches and the tag arrays. The design is constrained by the need to minimize area overhead while providing high test coverage and rapid at-speed testing. The solution encompasses a novel state machine design built using logic synthesis tools. This paper presents the RAM BIST design implemented on the PowerPC 603 microprocessor.