Benoit A. Gennart

dblp:59/2680 · DBLP profile ↗
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5ranked-venue papers
2as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 32% Parallel and multicore computing · 25% Storage systems · 25%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Medical and health informatics · 100%

Topics — the 7 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel computing › parallel software engineering
parallel application development
0.011999
Computer-aided parallelization of continuous media applications: the 4D beating heart slice server · ACM Multimedia (1) 1999
Storage systems › file systems › distributed file system
parallel file system
0.011999
Computer-aided parallelization of continuous media applications: the 4D beating heart slice server · ACM Multimedia (1) 1999
Electronic design automation › hardware verification and test
design validation
0.011993
Comparative Design Validation Based on Event Pattern Mappings · DAC 1993
Electronic design automation › hardware verification and test
hardware verification
0.011993
Comparative Design Validation Based on Event Pattern Mappings · DAC 1993
Performance modeling and evaluation
simulation
0.011992
Validating Discrete Event Simulations Using Event Pattern Mappings · DAC 1992
Electronic design automation › hardware verification and test
formal verification
0.011988
Verification of VHDL Designs Using VAL · DAC 1988
Electronic design automation
hardware verification and test
0.011988
Verification of VHDL Designs Using VAL · DAC 1988

Methods — techniques the papers use, named apart from their topics

token-based dataflow · 0.0pipelined parallel disk access · 0.0VAL · 0.0
YearPublicationVenuePosition
1999 Computer-aided parallelization of continuous media applications: the 4D beating heart slice server
abstract
Parallel servers for I/O and compute intensive continuous media applications are difficult to develop. A server application comprises many threads located in different address spaces as well as files striped over multiple disks located on different computers. The present contribution describes the construction of a continuous media server, the 4D beating heart slice server, based on a computer-aided parallelization tool (CAP) and on a library of parallel file system components enabling the combination of pipelined parallel disk access and processing operations. Thanks to CAP, the presented architecture is concisely described as a set of threads, operations located within the threads and flow of data and parameters (tokens) between operations. Continuous media applications are supported by allowing tokens to be suspended during a period of time specified by a user-defined function. Our target application, the 4D beating heart server supports the extraction of freely oriented slices from a 4D beating heart volume (one 3D volume per time sample). This server application requires both a high I/O throughput for accessing from disks the set of 4D sub-volumes (extents) intersecting the desired slices and a large amount of processing power to extract these slices and to resample them into the display grid. With a server configuration of 3 PCs and 24 disks, up to 7.3 slices can be delivered per second, i.e. 43 MB/s are continuously read from disks and 4.1 MB/s of slice parts are extracted, transfered to the client, merged, buffered and displayed. This performance is close to the maximal performance deliverable by the underlying hardware. The observed single stream server delay jitter varies between 0.6s (52% of maximal display rate) and 1.4s (92% of the maximal display rate). For the same resource utilization, the jitter is proportional to the number of streams that are accessed synchronously.
Joaquín Tárraga Giménez, Vincent Messerli, Oscar Figueiredo, Benoit A. Gennart, Roger D. Hersch
ACM Multimedia (1)4
1997 Performances of the PS2 Parallel Storage and Processing System for Tomographic Image
abstract
We propose a new approach for developing parallel I/O- and compute-intensive applications. At a high level of abstraction, a macro data flow description describes how processing and disk access operations are combined. This high-level description (CAP) is precompiled into compilable and executable C++ source language. Parallel file system components specified by CAP are offered as reusable CAP operations. Low-level parallel file system components can, thanks to the CAP formalism, be combined with processing operations in order to yield efficient pipelined parallel I/O and compute intensive programs. The underlying parallel system is based on commodity components (PentiumPro processors, Fast Ethernet) and runs on top of WindowsNT. The CAP-based parallel program development approach is applied to the development of an I/O and processing intensive tomographic 3D image visualization application. Configurations range from a single PentiumPro I-disk system to a four PentiumPro 27-disk system. We show that performances scale well when increasing the number of processors and disks. With the largest configuration, the system is able to extract in parallel and project into the display space between three and four 512/spl times/512 images per second. The images may have any orientation and are extracted from a 100 MByte 3D tomographic image striped over the available set of disks.
Vincent Messerli, Benoit A. Gennart, Roger D. Hersch
ICPADS2
1993 Comparative Design Validation Based on Event Pattern Mappings
abstract
Article Free Access Share on Comparative design validation based on event pattern mappings Author: Benoit A. Gennart View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 373–378https://doi.org/10.1145/157485.164936Published:01 July 1993Publication History 0citation186DownloadsMetricsTotal Citations0Total Downloads186Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
Benoit A. Gennart
DAC1
1992 Validating Discrete Event Simulations Using Event Pattern Mappings
Benoit A. Gennart, David C. Luckham
DAC1
1988 Verification of VHDL Designs Using VAL
Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu
DAC2