Monitoring the displacement of tailings dam landslides is a pressing technical challenge in the mining industry. Traditional monitoring solutions relying on integrated air-ground-space surveillance and multi-sensor data fusion have prominent shortcomings, including high costs and excessive energy consumption. To tackle this problem, this paper presents a self-powered ultra-wideband (UWB) landslide displacement monitoring system for tailings dams, which integrates solar energy and radio frequency (RF) energy in a coordinated manner. The system is composed of fixed base stations and mobile tags: the fixed base stations are powered by solar panels and are capable of transmitting RF energy, sending and receiving ultra-wideband positioning signals, and calculating positioning data; the mobile tags are designed as passive devices that can receive RF energy and send and receive positioning signals to transmit surface displacement information of the dam body. Experimental results demonstrate that the system can effectively transmit surface displacement data of the dam body, verifying the feasibility of the technology. By innovatively adopting a passive tag design and a solar-powered supply scheme, the system completely eliminates reliance on external power sources. This research provides an economical and efficient new technical solution for tailings dam safety monitoring.

Modeling and analyzing multiphysics effects has become one of the most challenging issues in integrated circuit design. Equivalent thermal circuit method is one of the most commonly used method in circuit design to simulate the electrothermal coupling effects, since it is fast and compatible with SPICE. However, it is still difficult to realize electro-thermalmechanical coupling simulation based on equivalent circuit method due to a lack of equivalent mechanical circuit method, which brings difficulties to do electro-thermal-mechanical analysis by SPICE. The equivalent mechanical circuit method is proposed based on solid mechanics equilibrium equation by deriving the electro-mechanical equivalent relation, equivalent circuit elements, equivalent circuit structure, equivalent circuit boundary condition, and the solving algorithm. The equivalent multiphysics circuit of TSV and FinFET are then further constructed to simulate the electro-thermal-mechanical coupling effects and verified with simulation results obtained from the finite element method (FEM). The results show that our proposed equivalent multiphysics circuit framework is able to simulate the electro-thermal-mechanical coupling effects by SPICE in integrated circuits.

Piezoelectric energy harvesting interfaces are mainly categorized into single-stage conversion interfaces with high efficiency and cascaded conversion interfaces with high output power. However, the single-stage conversion interface has limited output power and lacks an MPPT configuration, while the cascaded conversion interface suffers from low end-to-end harvesting efficiency due to the cascaded conversion process. This paper proposes a load-independent Split-S-SSHI (SS-SSHI) interface with an envelope-tracking MPPT that can simultaneously achieve high output power and high end-to-end efficiency. In addition, the split S-SSHI eliminates the need for a rectifier capacitor and enhances the response speed of the MPPT. The proposed harvester is fabricated in a 0.18-$\mu $m CMOS process with a low quiescent current of 39 nA. Measurements indicate a maximum MPPT efficiency and end-to-end harvesting efficiency up to 99.5% and 91.9%, respectively, and the maximum output power reaches 9.7 times that of a conventional full-bridge rectifier.

The non-ideal effects in resistive random-access memory (RRAM) crossbar arrays have become a critical factor limiting the computational accuracy of in-memory computing (IMC) circuits. In this work, we develop a comprehensive circuit model that integrates the electro-thermal effects of devices and the parasitic effects of interconnects, and the model is utilized to implement parallel computing for a two-layer$197\times 40\times 20$neural network. The combined impact of electro-thermal effect, IR drop, and parasitic crosstalk on the image recognition accuracy of Modified National Institute of Standards and Technology database (MNIST) dataset under different numbers of resistance states is evaluated. To address voltage attenuation caused by the line resistance of interconnects, a position-aware voltage loss prediction and correction scheme is proposed. This scheme dynamically adjusts the resistance distribution based on the prediction model determined by test data to calibrate the output current. Finally, an improvement scheme is proposed to reduce voltage trend errors caused by resistance degradation during the correction process, which provides an effective solution for the performance simulation and optimization of high-precision IMC systems.

The independence of logic optimization and technology mapping poses a significant challenge in achieving high-quality synthesis results. Recent studies have improved optimization outcomes through collaborative optimization of multiple logic representations and have improved structural bias through structural choices. However, these methods still rely on technology-independent optimization and fail to truly resolve structural bias issues. This paper proposes a scalable and efficient framework based on Mixed Structural Choices (MCH). This is a novel heterogeneous mapping method that combines multiple logic representations with technology-aware optimization. MCH flexibly integrates different logic representations and stores candidates for various optimization strategies. By comprehensively evaluating the technology costs of these candidates, it enhances technology mapping and addresses structural bias issues in logic synthesis. Notably, the MCH-based lookup table (LUT) mapping algorithm set new records in the EPFL Best Results Challenge by combining the structural strengths of both And-Inverter Graph (AIG) and XOR-Majority Graph (XMG) logic representations. Additionally, MCH-based ASIC technology mapping achieves a $3.73 \%$ area and $8.94 \%$ delay reduction (balanced), 20.35% delay reduction (delay-oriented), and $\mathbf{2 1. 0 2 \%}$ area reduction (area-oriented), outperforming traditional structural choice methods. Furthermore, MCH-based logic optimization utilizes diverse structures to surpass local optima and achieve better results.

Serverless edge computing seamlessly integrates edge computing with serverless computing, not only overcoming the limitations of resource-constrained edge nodes but also alleviating the high latency associated with cloud response. Due to the elastic scalability of serverless computing platforms, the cold start of latency-sensitive serverless functions (SFs) has become a significant challenge. Traditional strategies, such as resource reservation and prewarming, often suffer from low resource utilization. Meanwhile, offloading-based approaches simplify the problem by assuming a fixed high cold start delay cost, which is unsuitable for heterogeneous serverless edge computing scenarios. This paper proposes a Cold-Start aware offloading by double-dueling-DQN (CSODQN) model for SFs in a cloud-edge-device serverless computing system. The model creates an instance warming pool for SFs to enable reuse and allocates edge service node resources based on the priority of user and SFs, achieving multi-objective offloading optimization that considers cold starts. Our goal is to balance the frequency of cold start and resource utilization. To address the partially observable offloading optimization problem among agents, we employ a multi-agent deep reinforcement learning approach. By introducing an priority of action based sampling strategy, we accelerate the convergence of learning for each agent. Simulation results demonstrate that our method improves task success rates, reduces average task latency and cold start occurrences, and enhances resource utilization. Our approach alleviates the frequency of cold starts without excessively consuming system resources and costs, achieving long-term optimization of service quality, device energy consumption, and expenses.

This paper introduces a novel circuit simulator of k-input lookup table (k-LUT) networks, based on semi-tensor product (STP). STP-based simulators use computation of logic matrices, the primitives of logic networks, as opposed to relying on bitwise logic operations for simulation of k- LUT networks. Experimental results show that our STP-based simulator reduces the runtime by an average of 7.2 ×. Furthermore, we integrate this proposed simulator into a SAT sweeper. Through a combination of structural hashing, simulation, and SAT queries, SAT sweeper simplifies logic networks by systematically merging graph vertices from input to output. To enhance the efficiency, we used STP-based exhaustive simulation, which significantly reduces the number of false equivalence class candidates, thereby improving the computational efficiency by reducing the number of SAT calls required. When compared to the state-of-the-art SAT sweeper, our method demonstrates an average 35% runtime reduction.

Currently, the automatic management of roadside parking space remains a significant challenge. Installing cameras next to each roadside parking space is an extremely expensive solution. Utilizing Bluetooth beacons to identify vehicles requires the installation of a Bluetooth device on each vehicle. This not only necessitates vehicle power supply but also poses installation difficulties. Additionally, the Bluetooth devices installed on parking space need to operate for extended periods, consuming a significant amount of electrical energy and requiring grid power supply. To reduce system costs, alleviate installation difficulties, and achieve complete autonomy in power supply, this article proposes a solar-powered and radio frequency (RF) energy transmission-based Internet of Things (IoT) management system for roadside parking space. We have designed both the mobile and fixed terminal of the system. The fixed terminal is powered by solar panels, enabling it to emit RF energy, retrieve vehicle information, automatically track time, and upload data. The mobile terminal is designed as a passive device capable of receiving RF energy and transmitting vehicle information. Through experimental testing, the system successfully achieves automatic retrieval and upload of vehicle information and parking duration, thereby validating the feasibility of the proposed system. Since the mobile terminal is a passive device and the fixed terminal is powered by solar panels, no external power supply is required. This project introduces for the first time the utilization of solar energy conversion into RF power supply, enabling the mobile terminal to function as a passive device without the need for external power or internal batteries.

Boolean satisfiability (SAT)-based exact synthesis has made significant progress in recent years, particularly in logic rewriting for the identification of potential subnetwork replacements. However, existing rewriting algorithms suffer from two major drawbacks: 1) inflexibility due to precomputed potential replacement candidates and 2) high-computational complexity of off-the-shelf conjunction normal form (CNF)-based SAT solvers. In this article, we propose a novel semi-tensor product (STP)-based exact synthesis approach for logic rewriting. The STP-based exact synthesis encodes Boolean functions into logic matrices and uses circuit-based all solutions SAT (AllSAT) solver to obtain all optimal replacement candidates with a single pass. Additionally, we improve the subnetwork selection strategy to allow flexible rewriting by selecting the most cost-effective implementation of all optimal candidates. Experimental results, compared with the state-of-the-art logic synthesis tool ABC, show that proposed STP-based exact synthesis reduces 41% runtime on average and solves all instances within a time limit. Moreover, after mapping into 6-LUT FPGA technology and standard cells, we obtain average improvements in the area of 6% and 18%, respectively.

In this paper, a mutually synergistic hybrid energy harvesting (SHEH) circuit with both AC and DC energy harvesting capability is proposed. Within the proposed hybrid harvester, the vibration period of the piezoelectric transducer (PZT) is served as the switching signal for photovoltaic (PV) energy harvesting so that a dedicated clock generator is saved. Meanwhile, during the sampling phase, a small portion of the PV energy is injected into the PZT as an investment, which enhances the damping force and charge extraction of the PZT. Theoretically, the total synergistically extracted power from the proposed hybrid harvester is more than the sum of the power obtained from each transducer independently. The proposed SHEH circuit is fabricated with a 0.18-$\mu \text{m}$CMOS process. The buck-boost converter with zero-current switching control achieves a peak efficiency of 82.8%, and the maximum efficiency of piezoelectric energy harvesting can reach 4.5 times that of the full-bridge rectifier.

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.

Approximate computing (AC) offers benefits by reducing the requirement for full accuracy, thereby reducing power consumption and area. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. In this article, ML-based arithmetic circuits, i.e., multibit adders and multipliers, are proposed. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. Several logic implementation costs, error metrics, and layouts implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous ML-based designs based on the experimental results. The proposed designs are further evaluated using both a neural network (NN) accelerator and image processing. A structural similarity (SSIM) value of 1 and a peak signal-to-noise ratio (PSNR) value of infinity are achieved by the proposed adder design.

CMOS/nanowire/molecular hybrid (CMOL) circuit has a considerable number of defective nanodevices during manufacturing, therefore, the defect-tolerant cell mapping is critical for the logic implementation in CMOL architecture. To the best of our knowledge, the impact of defects on the performance of mapped circuits has not been intensively explored. This paper analyzes two factors influencing the delay of mapped circuits: the CMOL circuit defects and the traditional defect-tolerant mapping methods. And a defect-tolerant method aiming at optimizing the delay of the mapped circuit is proposed. To this end, a signal path segmentation method and directed mapping method that fully considers the delay among mapping gates are utilized. The experiment results on the ISCAS benchmarks shows that our method improves the delay by 14.4% than the state-of-the-art approaches.

Typical operators for the decomposition of Boolean functions in state-of-the-art algorithms are AND, exclusive-OR (XOR), and the 2-to-1 multiplexer (MUX). We propose a logic decomposition algorithm that uses the majority-of-three (MAJ) operation. Such a decomposition can extend the capabilities of current logic decompositions, but only found limited attention in the previous work. Our algorithm make use of a decomposition rule based on MAJ. Combined with disjoint-support decomposition, the algorithm can factorize XOR-majority graphs (XMGs), a recently proposed data structure which has XOR, MAJ, and inverters as only logic primitives. XMGs have been applied in various applications, including: 1) exact-synthesis-aware rewriting; 2) preoptimization for 6-input look-up table (6-LUT) mapping; and 3) synthesis of quantum circuits. An experimental evaluation shows that our algorithm leads to better XMGs compared to state-of-the-art algorithms based on XMGs, which positively affects all of these three applications. As one example, our experiments show that the proposed method achieves an average of 10% and 26% reduction on the LUTs size/depth product applied to the EPFL arithmetic and random control benchmarks after technology mapping, respectively.

In this paper, we present a structural rewriting method for a recently proposed XOR-Majority graph (XMG), which has exclusive-OR (XOR), majority-of-three (MAJ), and inverters as primitives. XMGs are an extension of Majority-Inverter Graphs (MIGs). Previous work presented an axiomatic system, Ω, and its derived transformation rules for manipulation of MIGs. By additionally introducing XOR primitive, the identities of MAJ-XOR operations should be exploited to enable powerful logic rewriting in XMGs. We first proposed two MAJ-XOR identities and exploit its potential optimization opportunities during structural rewriting. Then, we discuss the rewriting rules that can be used for different operations. Finally, we also address structural XOR detection problem in MIG. The experimental results on EPFL benchmark suites show that the proposed method can optimize the size/depth product of XMGs and its mapped look-up tables (LUTs), which in turn benefits the quantum circuit synthesis that using XMG as the underlying logic representations.

Recent studies show that majority-based logic synthesis is beneficial for both traditional and nanotechnology digital designs. However, most of the existing synthesis algorithms for majority logic generate majority-of-three (M3) networks. The optimization opportunity for majority logic by using an arbitrary number of odd inputs still requires a large research effort. In this paper, we present an exact synthesis approach for computing Boolean functions in majority-of-five (M5) forms with a minimum number of operations using Boolean satisfiability. By exploiting the symmetry properties of majority operators, we make use of symbolic encoding method to represent the node functionality and to reduce the number of variables. Moreover, we represent the M5forms by M5-inverter graphs (M5IGs) for manipulation, which is an extension of majority-inverter graphs (MIGs). The experimental results on EPFL benchmark suites indicate the proposed method achieves 10.4% improvement on size and 11.4% on depth compared to the state-of-the-art exact synthesis method.

Placement has always been the most time-consuming part of the field programmable gate array (FPGA) compilation flow. Conventional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes an adaptive range-based algorithm to improve the behavior of swap operations and limit the swap distances by introducing the concept of range-limiting strategy for nets. It avoids unnecessary design space exploration, and thus can converge to near-optimal solutions much more quickly. The experimental results are based on the Titan benchmarks, which contain 4K to 30K blocks, including logic array blocks, inputs and outputs, digital signal processors, and random access memories. This approach achieves$2.82\boldsymbol \times $speed up, 4.8% reduction on wire length, 4.1% improvement on critical path compared with the SA from VTR with wire length-driven optimization, and$1.78\boldsymbol \times $speed up, 10% reduction on wire length, 2% reduction on critical path with path timing-driven optimization. It also manifests better scalability on larger benchmarks.

Using coaxial through-silicon technologies, a new 3-D capacitor integrated on a silicon interposer is proposed. The capacitance of coaxial through silicon via (CTSV) capacitors is extracted, analyzed, and compared. The results obtained from the analytical model and the finite-element method exhibit good agreement with various design parameters, and the error between the proposed model and measurement remains less than 7.41%. Due to high capacitance density up to 22.4 nF/mm2, the 3-D capacitor is adopted as a decoupling capacitor for the on-chip low-dropout (LDO) regulator design. The proposed LDO is developed in a 180-nm CMOS technology and shows unique advantages regarding the power supply rejection (PSR) performance, quiescent current, and area compared with that of the conventional LDOs with off-chip capacitors and capacitor-less (CL) LDOs.

Typical operators for the decomposition of Boolean functions in state-of-the-art algorithms are AND, exclusive-OR (XOR), and a 2-to-1 multiplexer (MUX). We propose a logic decomposition algorithm that uses the majority-of-three (MAJ) operation. Such decomposition can extend the capabilities of current logic decomposition, but only found limited attention in previous work. Our algorithm makes use of a decomposition rule based on MAJ. Combined with disjoint-support decomposition, the algorithm can factorize XOR-Majority Graphs (XMGs), a recently proposed data structure which has XOR, MAJ, and inverters as only logic primitives. XMGs have been applied in various applications, including (i) exact synthesis aware rewriting, (ii) pre-optimization for 6-LUT mapping, and (iii) synthesis of quantum networks. An experimental evaluation shows that our algorithm leads to better XMGs compared to state-of-the-art algorithms, which positively affect all these three applications. As one example, our experiments show that the proposed method achieves up to 37.1% with a average of 9.6% reduction on the look-up tables (LUT) size/depth product applied to the EPFL arithmetic benchmarks after technology mapping.

This paper models and studies silicon-core coaxial through silicon vias (CTSVs), in which the metal via is replaced with a Cu coated silicon pole. Based on the physical structure of CTSVs, the impact of various design parameters on the electrical performance is investigated. It is shown that the high frequency loss of CTSVs is dominated by the dielectric and the increase in the thickness of plated Cu decreases the CTSV insertion loss. Furthermore, a set of analytical formulas are presented to capture the equivalent resistance-inductance-capacitance-conductance (RLCG) parameters of CTSVs, it yields accuracy results comparable to those with a commercial full-wave simulator. Finally, a comparison of the proposed CTSVs with other two TSV structures is carried out to demonstrate the feasibility of the silicon-core CTSVs in future three-dimensional (3D) integration.

Placement has always been the most time-consuming part in the FPGA compilation flow. Traditional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes a range-based algorithm to improve the behavior of swap operations and limit the swap distances by introducing the concept of range limiting for nets. It avoids unnecessary design space exploration, and thus can converge to near-optimal solutions much more quickly. The Titan benchmarks we have tested on contains 4K to 30K blocks, which include LABs, IOs, DSPs and RAMs. This approach achieves 2.05X speed up on average compared with the SA from VTR while preserving the placement quality of both the wire length and critical path. It also manifests better scalability towards larger benchmarks.

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for general logic that is poor in arithmetic operations. Recently, Majority-Inverter Graphs (MIGs) were proposed for efficient Boolean logic optimization. MIGs open an opportunity for efficient mapping of critical paths onto hard carry chains, as the carry logic of a full adder is naturally a majority (MAJ) gate. In this paper, we propose an MIG-based synthesis method to exploit hard adders in FPGAs for the mapping of general logic. The proposed heuristic algorithm selects MAJ nodes to be mapped on the carry chains and the associated LUTs; then, the efficiency of carry chain mapping is examined theoretically for efficient LUT utilization. The experimental results show that, compared to traditional design flow Verilog-to-Routing (VTR 7.0), the proposed approach can improve delay by up to 25% with an average of 8%, while the channel width is reduced by up to 20% with an average of 6%.

To implement multi-voltage technique in SoC designs, level shifters (LSs) are essential modules which translate signals among different voltage domains. However, inserting LSs requires non-negligible area and timing overhead. In this paper, we study LS planning (LSP) method for timing constrained multi-voltage SoC floorplanning problem. The design flow consists of two phases. In phase I, to reserve the desired white space for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. In phase II, the main floorplanning loop is implemented. Different from previous works which do voltage assignment without physical information feedback, we build an inner loop between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 15% with 4% area increase.

Multi-voltage technique is an effective way of power saving in system-on-a-chip (SoC) designs. However, as the technology nodes continue to shrink, the voltage drop constraint in multiple power domains presents serious obstacles in power/ground (P/G) network design of wire-bonding package. In this paper, a voltage drop aware power pad assignment and floor planning method for multi-voltage SoC designs is proposed. In order to reduce the voltage drop, we develop a fast method to calculate the location of power pad for each power domain based on the spring model. During floor planning iterations, a static voltage drop analysis is performed to update the voltage drop distribution, and then number of violation nodes in the P/G network is obtained. To speed up the floor planning algorithm, instead of time-consuming matrix computation to obtain voltage drops, we use the weighted distance from blocks to power pads as an optimization objective. Experimental results on GSRC benchmark suites indicate that the proposed approach generates an optimized placement of power pads and floor planning of blocks.

Based on the disjointed products and by using logic decomposition techniques, a logic function's cover is divided into two parts which are suitable for RM logic implementation and Boolean logic implementation respectively. Then the function is minimized with both RM logic and Boolean logic (dual logic) at the same time. Further, a method of the functional verification for dual logic is also proposed by checking whether the covers of two functions are equal or not. The proposed minimization algorithm is implemented in C and tested on MCNC benchmarks. The experimental results show that for the most test cases the proposed dual logic minimization algorithm produces less products compared with that of ESPRESSO.

By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table, an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM function by searching for and extracting the common variables using the onset table. Furthermore, by employing the multiplexer model, the algorithm is extended to optimize multi-level multi-output mixed-polarity RM forms. The proposed algorithm is implemented in C language and tested using some MCNC benchmarks. Experimental results show that the proposed algorithm can obtain a more compact RM form than that under fixed polarity. Compared with published results, the proposed algorithm makes a significant speed improvement, with a small increase in the number of literals.

This paper considers a cell mapping task of CMOL, a hybrid CMOS/molecular circuit architecture. To tackle the combinatorial hurdle arising from the structural connectivity domain constraint, a memetic computing algorithm is developed. The framework takes advantage of simulated annealing based local search strategy and appropriate population based encoding manipulation. Numerical results from ISCAS benchmarks and comparison with pure genetic approach illustrate the effectiveness of the modeling and solution methodology. In terms of CPU runtime, timing delay and circuit scale, the proposed method has better performance than previous methods.

In this paper, polarity transform is introduced to identify low power XOR gate decompositions. It is pointed out that the previous solutions for XOR gate decomposition are not optimal. Based on searching best polarity for low power dissipation, a new algorithm is proposed and implemented in C. The experimental results show improved switching activities compared with previous publications.