This paper extends the low-temperature modeling capabilities of an industry-standard compact metal-oxide-semiconductor field-effect transistor (MOSFET) model by incorporating physics-based representations of cryogenic effects in semiconductors. Specifically, the incomplete dopant ionization effect is integrated into the bulk Fermi potential calculation of the compact model and applied as a threshold voltage shift in the formulation of Poisson's equation. Temperature-related models for bandgap energy, saturation velocity, and contact resistance at the source/drain regions are also enhanced. Using transistors fabricated with 22 nm process technology, we demonstrate that this consistent modeling approach accurately reproduces current-voltage and threshold voltage-temperature characteristics across a temperature range from 300 K to 4 K.

Two types of ring oscillators (ROs) fabricated using a 65 nm FD-SOI process were used to compare total ionizing dose (TID) characteristics under gamma-ray and alpha-ray irradiation. By employing two ROs with nearly identical circuit structures, the electric field dependence of the TID effect was evaluated. Gamma-ray irradiation resulted in significant degradation differences between the ROs, indicating strong electric field dependence, whereas alpha-ray irradiation showed negligible differences, suggesting weak dependence. These variations are attributed to differences in initial recombination rates due to the higher linear energy transfer (LET) of alpha particles than gamma-rays. Additionally, the recovery rate under alpha-ray irradiation was lower than that under gamma-ray irradiation. These findings suggest that when using alpha-ray irradiation as an alternative to gamma-ray irradiation, compensation is mandatory.

To realize a fault-tolerant quantum computer, a quantum error decoder that can handle a large number of qubits with high speed is required. This paper demonstrates an ASIC implementation of a quantum error decoder based on a greedy algorithm. The simple algorithm and microarchitecture enable a low-power and compact design. A test chip is fabricated using 22-nm CMOS technology, and its operation is verified through empirical evaluation.

In 22 nm FDSOI, the flip-well structure is used instead of the standard-well structure. We evaluated soft-error tolerance by heavy-ion irradiation tests on standard and stacked flip-flops (STDFF and STACKEDFF) in the flip-well structure. The error probability of STACKEDFF was significantly smaller than STDFF. Therefore, the stacked structure is also effective against soft error in the flip-well structure. However, as the supply voltage is lowered, even STACKEDFF becomes vulnerable to soft errors under certain conditions. The origin of these errors was pMOSFETs. Therefore, soft error countermeasures are needed to account for errors from pMOSFETs.

We examined the radiation hardness of the several types of flip-flops fabricated in a 130 nm bulk process by alpha-ray irradiation tests and circuit simulation. The simulated $\alpha -$SER of FFs with the critical charge larger than 14 fC becomes 1/100 of that with the critical charge of 10 fC. We propose a radiation-hardened flip-flop minimizing area, delay, and power overheads with 1/100 lower $\alpha -$SER in a 130 nm bulk process. The radiation hardness is achieved by adding series transistors and wires with only less than 14% area, 7% delay, and 12% power overheads in order to increase the critical charge. Alpha-ray irradiation tests revealed that the proposed method can reduce soft error rates to 1/100.

Embedded static random access memories (SRAMs) with cost-effective test screening circuitry are demonstrated for low-power microcontroller units (MCUs). The probing test step at the low temperature (LT) of -40 °C is obviated by imitating pseudo-LT (PLT) conditions in the package test, where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out considering local Vtvariations as well as contact soft open failure (high resistance), confirming good minimum operating voltage ( Vmin) correlation between LT and PLT conditions. Test chips with two types of 4-Mbit single-port SRAM macros and 1-Mbit dual-port SRAM macro are designed and fabricated using low-power 40-nm CMOS technology. Measurement results demonstrate that the proposed test method reproduces LT conditions and screens out LT failures with less overscreening. The proposed test method eliminates 1/3 or more of the test costs.

An accurate metric for the time step control in the power device transient simulation is proposed. This metric contains an exponential term of the dominant time constant of the whole device structure derived from the matrix exponential term of the linearized device state equation. The proposed metric allows larger time step widths than the conventional metric of second order approximation of the local truncation error. It focuses on the dominant part of the transient response and its truncation error approximation is more accurate. In the transient device simulation, box integration method and backward Euler method are used for spatial and temporal discretization, respectively. The discretized nonlinear device equations are solved by using Newton iteration whose initial guess is given by the approximated solution of the linearized device state equation by using the dominant time constant. Total calculation time of the transient simulation of a silicon power DMOSFET by using the proposed method decreases down to 27% of that by the conventional method with keeping the current accuracy of the dominant transient response.

We examined radiation hardness of a stacked transmission-gate flip flop and a stacked tristate-inverter flip flop, which are called STACKEDTGFF and STACKEDTIFF respectively. Stacked flip flops fabricated in FDSOI are stronger against soft errors than in bulk because all transistor channels are isolated by a BOX layer. We evaluated soft-error tolerance by neutron and heavy-ion irradiation. STACKEDTIFF is faster than STACKEDTGFF because of the difference of the number of gates along the data path. Those FFs did not flip by neutrons and the normal incidence of heavy ions with LET of less than 40 MeV-cm2mg. They are stronger against soft errors than a standard TGFF by two order of magnitude. We also investigated incident angle dependence of those FFs by heavy ions.

In this paper, simple and compact Negative Bias Temperature Instability (NBTI) model is proposed. The model is based on the reaction-diffusion (tn) and hole-trapping (log(t)) theories. A single shot of DC stress and recovery data is utilized to express duty cycle dependence of NBTI degradation and recovery. Parameter fitting is proceeded by considering that the amount of recovery cannot be larger than stress degradation. The proposed model successfully replicates stress and recovery with various duty cycles.

Total ionizing dose (TID) effect is a phenomenon that threatens the reliability of transistors under high-radiation environments. TID is caused by radiation-induced trapped holes in oxide insulator. We evaluated the effects of TID on fully-depleted silicon on insulator (FDSOI) and bulk processes by measuring frequency of a ring oscillator (RO) and single event upset tolerance of flip flops (FFs). On the bulk process, TID induced Vth shift of nMOSFET, leads to increase of the RO frequency. On the FDSOI process, IR drop induced by large amount of leakage current flowing above buried oxide (BOX) layer decreases RO frequency. We also demonstrated that TID effects recovers by thermal annealing.

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.

Presents a conference poster that addresses a perpetuum mobile 32bit central processing unit that resides on 65nm CMOS technology using reverse-body-bias via assisted sleep mode.

We fabricated a 65nm LSI including flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. It consists of two FF arrays as follows. One is an array composed of redundant FFs to confirm radiation hardness of the proposed and conventional redundant FFs. The other is an array composed of conventional D-FFs to measure SEU (Single Event Upset) and MCU(Multiple Cell Upset) by the distance from tap cells.

We show NBTI delay degradation considering variations in a 65 nm process. We evaluate these two models. The homogeneous degradation model (HDM) assumes that NBTI degradation is constant at any variation and the inhomogeneous degradation model (IDM) assume that it is larger at the fast condition. In the usual logic gates on ASICs, delay degradation becomes much smaller on IDM. Circuit design guardbands can be reduced to 1/3 from the conventional pessimistic evaluations. As for FPGAs, we evaluate routing paths including level restorers and tristate inverters. The delay time after NBTI degradation is almost constant because of the pull-up PMOS in the level restorer.

In this paper, we proposed a light-weighted recovery scheme for fault tolerable pipeline processors after error has been detected by redundant executions. A minimal rolling back procedure is designed to schedule the re-execution based recovery in a one-cycle delay. This scheme makes full use of in-fly pipeline working status to aid the recovery, which relieves the recovery from a large checkpoint buffer.

Error rates on an LSI are increasing according to the Moore’s law. Now is the time to start incorporating error-tolerant design methodologies. This paper introduces sources of failures in semiconductor devices, levels of dependability according to applications of devices and some circuit-level techniques to detect or recover faults after shipping.

FPGAs in future deep submicron fabrication process will suffer from drastic speed and yield loss caused by device variations. We propose variation-aware reconfiguration which utilizes variations for performance enhancement. To utilize random variations for performance enhancement, optimizing each device from a common initial configuration is better than producing optimized configurations according to detailed measurement results because it is very hard to measure detailed variation maps chip by chip when random uncorrelated variations are dominant. In the critical path reconfiguration scheme, an initial configuration is gradually optimized chip by chip according to the delay variations. We apply the track swapping procedure to critical path reconfiguration which obtains an optimized configuration to repeat measurement and reconfiguration. First we configure all fabricated FPGAs with a common configuration data without considering variations. The configuration of each die is optimized to reroute the critical paths by choosing a faster path. To reroute a critical path we swap a wire track on a critical path with the adjacent track. It can be realized to use switch blocks with more flexibility. We implement the track swapping to VPR and experiment performance enhancement by applying the track swapping to LGSynth93 benchmark circuits. The average speed and yield enhancements are 2.57%, 26.01% respectively when the standard deviation of random variations is 10.0%

We propose a variation-aware post-fabrication optimization scheme on FPGAs. Variation-aware optimization usually takes huge measurement cost. The proposed scheme achieves a constant optimization cost for any circuit configuration. We utilize delay detectors embedded in clustered CLBs to choose fastest paths among multiple candidates. The delay detectors enable simultaneous measurement of critical path candidates to partition all critical paths into segments. The number of measurement to choose fastest paths on all critical paths does not depends on configurations but on FPGA architectures. We confirm that a simple heuristic algorithm can find the order of measurement near the lowest bound of the measurement cost and it is almost constant regardless of circuit configurations.

Since FPGAs in future deep sub-micron processes will suffer from drastic speed and yield losses caused by device variations, we propose variation-aware reconfiguration that utilizes these variations for performance enhancement. To utilize random variations on a current deep submicron process for performance enhancement, optimizing each device from a common configuration is better than producing optimized configurations based on detailed measurement results. In this paper we apply a track swapping procedure to critical path reconfiguration. First, we configure all fabricated FPGAs with common configuration data. The configuration of each die is optimized to reroute the critical paths that do not satisfy timing specifications. The rerouting of a critical path usually causes serious topology changes that may prolong other paths and create new critical paths. In the track swapping procedure, we swap a wire track on a critical path for the adjacent track without any topology changes by switching blocks with more flexibility. We experiment on performance enhancement by applying track swapping to LGSynth93 benchmark circuits. The average speed enhancement is 2.45%, and the average yield enhancement is 32.7% when the standard deviation of the random variations is 10.0%.

We have fabricated an LUT-based FPGA device with functionalities measuring within-die variations in a 90nm process. Measured variations are used to configure each device to maximize the operating frequency by allocating critical paths in faster portions. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Placement optimization using a simple model circuit reveals that performance of the circuit is enhanced by 4% in average, which is the same amount as the measured within-die variations. The yield is enhanced by 32% to the worst case.

It is possible to enhance speed and yield of reconfigurable devices utilizing WID variations. An LUT array LSI is fabricated on a 90nm process to measure WID and D2D variations. Performance fluctuations are measured by counting the number of LUTs through which a signal is passing within a certain time. D2D and WID variations are clearly observed by the measurement

A reconfigurable device can be utilized to enhance speed and yield on the sub-100nm device technologies, in which large within-die (WID) variations will degrade speed and cause huge yield loss in conventional fixed-structured ASICs. In the proposed scheme, configurations of all fabricated chips are optimized according to measured intra variations of LUTs and switch matrixes. Two LSIs are fabricated in a 90nm CMOS process. We successfully measured WID variations on the first LUT array LSI. The speed is enhanced by 4.1% in average on the second variation-aware FPGA LSIs to optimize configurations by the measured WID variations

We propose an area-efficient resource-shared VLIW processor (RSVP) for future leaky nm process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that waste power. The performance per power (P3) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P3 in the future 25nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180nm process. It is functional at 100MHz clock speed and its power is 130mW.

We propose a vector-pipeline processor VP-DSP for low-rate videophones, which can encode and decode 10 frames/sec. of QCIF through a 29.2kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 um CMOS process. The area of the VP-DSP core is 4.2mm. It works properly at 25MHz/1.6V with the power dissipation of 49mW. Its peak performance is up to 400MOPS, 8.2GOPS/W.

We propose a low bit-rate coding algorithm for wireless communication based on multi-stage hierarchical vector quantization, motion compensation and differential pulse code modulation. Our method adapts bit allocation to spatial and temporal correlation. Conventional schemes based on the discrete cosine transform (DCT) need a large amount of computation on both encoding and decoding. On the other hand, our proposed method consists of addition, subtraction and shift operation. It does not use multiplication. It can decode in real time on a conventional serial processor. Encoding by vector quantization (VQ), however, consumes a large amount of computation. We developed a new LSI to accelerate VQ. Our scheme can send 10 frames of QCIF video sequences through a 29.2 kbps line. The quality of reconstructed image is over 30 dB.

We propose a memory-based parallel processor for vector quantization, called a functional memory type parallel processor for vector quantization (FMPP-VQ). It accelerates the nearest neighbour search of vector quantization. All distances between an input vector and reference vectors in a codebook are computed simultaneously in all PEs. The minimum value of all distances is searched in parallel. The nearest vector is obtained in O(k), where k stands for the dimension of vectors. An LSI including four PEs has been implemented. It operates at 25 MHz clock frequency.