We present a new approach for FPGA testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without area or performance penalties to the system function implemented by the FPGA, since the FPGA is reconfigured for normal system operation. An analysis of Look-Up Table (LUT) based FGPA architectures yields a general expression for the number of test sessions and establishes the bounds on FPGA logic resources required to minimize the number of BIST configurations required to completely test all of the programmable logic blocks of an FPGA.

We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.

We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.