The growing variability and complexity of advanced CMOS technologies makes the physical design of clocked logic in large Systems-on-Chip more and more challenging. Asynchronous logic has been studied for many years and become an attractive solution for a broad range of applications, from massively parallel multi-media systems to systems with ultra-low power & low-noise constraints, like cryptography, energy autonomous systems, and sensor-network nodes. The objective of this embedded tutorial is to give a comprehensive and recent overview of asynchronous logic. The tutorial will cover the basic principles and advantages of asynchronous logic, some insights on new research challenges, and will present the GALS scheme as an intermediate design style with recent results in asynchronous Network-on-Chip for future Many Core architectures. Regarding industrial acceptance, recent asynchronous logic applications within the microelectronics industry will be presented, with a main focus on the commercial CAD tools available today.

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.

Laser-based fault injections are currently the most efficient technique that can be used to attack a secure system, since they have very high timing and location precision. Several papers have shown that a secret key may be recovered from ASICs and countermeasures have been proposed. But little research has been addressed at the specific case of secure protected implementations in SRAM-based FPGAs. This paper presents the results of laser-based fault injections on an architecture computing the AES encryption algorithm, protected by an error detection scheme, and implemented on a Virtex device. The results are compared to previous emulated fault injection campaigns and prove the criticality of remnant errors in the configuration of a FPGA used for secure applications. An improved countermeasure is also proposed and validated with a new experimental campaign.

Programmable devices like SRAM-based FPGAs, thanks to their low cost and high flexibility, are increasingly used for security applications; the mam drawback is their configuration memory, sensitive to perturbations. Symmetric cryptosystems are highly vulnerable to fault injections [1], but very few papers have reported laser-based fault attacks onto a secure implementation on a SRAM-based FPGA.

The C-element is a fundamental component in asynchronous circuits and quite used in synchronous circuits to mitigate transient faults. This work evaluates the transient-fault effects on the traditional dynamic, conventional, weak feedback, and symmetric C-element's implementations. An evaluation methodology is developed by means of fault-injection simulations at transistor level. Unlike existing methods, the methodology in this work is able to deal with the C-element function's particularities. In addition, C-element cells in different transient-fault robust versions are designed by using techniques based on sizing and transistor insertion. Results in terms of delay, power consumption, area, and fault-transient robustness show the best C-element options for the design of more robust systems.

A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the particularities of asynchronous circuits. Unlike previous works, it permits to compare the sensitivity of circuits designed by synchronous and asynchronous logics. The resultant metrics allow identifying at high-level abstraction what is the logic that makes the circuit more transient-fault sensitive. As a case study, a crypto-processor in versions synchronous and asynchronous was evaluated.

Ultra-low voltage is now a well known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting-up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. It performs at 457 kHz, with a total energy consumption of 2.9fJ per cycle.

SRAM-based FPGAs are an appealing platform to implement many systems, including secure ones. However, secure systems are subject to attacks and one of the main threats is fault-based attacks using lasers. The sensitivity of the configuration memory in a SRAM-based FPGA has to be studied in this context. This paper reports on the characterization of the effective laser spot, or effective sensitive area, with respect to the laser focus and to the attacked configuration bits. The test vehicle is a Virtex II FPGA. It is shown in particular that the initial value of the bit has a strong influence on the effective sensitive area of the spot. Such data can be used to better understand the actual effects of an attack and to design more efficient counter-measures. Also, it is shown that attacks based on single bit flips in the configuration are possible in practice even with relatively large laser spots.

On-chip digital oscillators are ubiquitous in every communication applications like in RF architectures or intra-chip communication systems. Actually, their integration to the standard CMOS design flow, their ability to generate high-frequency signals, as well as their configurability make them really attractive for designers. However, these kinds of digital oscillators suffer from their sensitivity to any process, voltage, or temperature variations. Self-timed systems are usually considered robust to these kinds of variations. This paper proposes the use of self-timed ring structures for generating high-resolution timing signals. One of the main difficulties when designing such oscillators is to avoid burst oscillating modes and produce uniformly spaced events in order to act as a periodic time-base. Based on a high-level ring model, enriched with stage switching timing information, the temporal behavior of oscillating self-timed rings is studied and their robustness to process variability is evaluated. Several ring architectures are explored to take advantage of complex combination of stages I/Os and it is shown that one can tune a tradeoff between oscillation period and signal stability. In addition, the paper provides designers with the ability to easily prevent burst oscillating modes by applying a very tractable ring design rule. Electrical simulations demonstrate the correctness and efficiency of the approach.

Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous studies presented the results obtained with multiple laser shots across different elements of the device. The exact effect of a single laser shot was not studied; a global picture of the type of generated errors was rather drawn. This work analyses the effects of a single laser shot onto the configuration memory. Results take into account several diameters of pulsed laser spots targeted on several types of logical blocks and compare theirs effects.

With the growing security needs of applications such as homeland security or banking, the frequent updates in cryptographic standards and the high ASIC costs, the ciphering algorithms on an asynchronous embedded FPGA co-processor are becoming a viable alternative. Within the SAFE project, a novel architecture of asynchronous e-FPGA has been proposed. This architecture is natively robust against side channel attacks such as simple and differential power analysis or clock based fault attacks. Simulation-based security proofs are also presented.

This work is a contribution to enhance the signal processing chain required in mobile systems. The system must be low power as it is powered by a battery. Thus a signal driven sampling scheme based on level crossing is employed, adapting the sampling rate and so the system activity by following the input signal variations. In order to filter the non-uniformly sampled signal obtained at the output of this sampling scheme a new adaptive rate FIR filtering approach is devised. The idea is to combine the features of both uniform and nonuniform signal processing tools to achieve a smart online filtering process. The computational complexity of the proposed approach is deduced and compared to one of the classical FIR filtering approach. It promises a significant gain of the computational efficiency and hence of the processing power.

Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of quasi delay insensitive (QDI) asynchronous circuits in the presence of SEUs (memory bit flips). The circuits and the fault injection process are both described using this model. The method, based on symbolic simulation, consists of exploring all the reachable states in the presence of faults in order to draw up an exhaustive list of behaviors. A case study shows that this method enables us to verify some properties on the circuits. SEU resistance can be formally proven using this analysis.

This paper presents ASC, an Asynchronous SystemC library, as an extension of SystemC for modeling asynchronous circuits. ASC includes a set of port and channel primitives offering the same communication primitives as the common languages used for asynchronous circuits modeling (CHP, Tangram or Balsa). ASC also offers operators and statements in order to accurately model arbiters, which are the basic components of asynchronous network on chips. The aim of this work is to provide to the designers the means of modeling and verifying asynchronous circuits as well as GALS and NoC systems. Synthesis of ASC models with the help of the TAST framework is under development. As an illustrative example, the modeling of an asynchronous network-on-chip architecture using the ASC library is described. This NoC has been successfully integrated into a complex GALS NoC architecture taking advantage of a multi-level SystemC based verification environment

The performances of continuous time delta sigma converters are severely affected by clock jitter and no generic technique to predict the corresponding degradations is nowadays available. This paper presents a new analytical approach to quantify the power spectral density of jitter errors. This generic computational method can be applied to all kind of delta sigma converters. Furthermore, clock imperfections are described by means of phase noise spectrum, consequently all possible type of jitters can be taken into account. This paper also describes the temporal non ideal clock models that have been created to simulate the impact of jitter on delta sigma converters and validate the theoretical results.

This paper presents practical results on the evaluation of fault countermeasures implemented in an asynchronous DES coprocessor. The theory underlying the countermeasures was previously published in IOLTS 2005. For the first time this work reports a practical evaluation of fault countermeasures applied on asynchronous DES ASICs. Two DES crypto processors were fabricated using the 130 nm STmicroelectronics CMOS process; one as a reference and one hardened using a specific technique. This work enables us to compare the resistance of both circuits against fault injection and to validate the proposed countermeasures. The practical set-up of the fault injection, using a laser, is presented and the test campaign described. The practical results prove the efficiency of the method. The techniques can be applied to protect logic blocks in any applications.

The problem of fault tolerance and fault resistance is becoming more and more important in all application fields. In this context, asynchronous designs provide inherent properties that make them attractive to design robust systems. Moreover, hardening techniques can be applied at the design time to improve their fault resistance with low area, speed and power costs. This work presents the latest characteristics analysis and conclusions on the potential of asynchronous circuits for both security and safety designs. It clearly demonstrates that the asynchronous technology enables the design of efficient fault tolerant/resistant integrated circuits

The integrated systems today require flexibility, performance and reconfigurability. The trends in this domain lead to integrate on a single chip different processing cores, communication units and reconfigurable logic. Therefore the systems-on-chip (SoC) can embed programmable logic. In order to challenge the reconfigurability paradigm for special issues such as communication, synchronization or security, the asynchronous logic is a very promising approach. Nevertheless, the standard programmable logic blocks are not well-suited to map asynchronous circuits. The goal of this study is to define a more adequate programmable structure to implement asynchronous designs on SoCs embedding a reconfigurable part. This work is part of a larger project which includes the design of an embedded programmable logic device (e-PLD) dedicated to the implementation of clockless circuits. The more robust and reliable asynchronous circuits are quasi-delay insensitive. These circuits are mainly constructed with Muller gates. The paper presents a new look-up table (LUT) architecture well-adapted to the Muller gate implementation. This new LUT allows the combination of a single memory-point with combinational logic. This programmable memory is realized thanks to an optional feedback structure. This architecture has been evaluated in CMOS, pass-transistor logic and 3-state logic which is a non-conventional way to design LUTs. The simulations report detailed comparisons between the different logic styles and demonstrate for equivalent power consumption a higher speed for 3-state logic

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust

This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they are an interesting alternative to design robust systems. A behavior diagnosis enables us to propose hardening techniques that improve fault tolerance and resistance. They are applied at design time and aim at exploiting quasi-delay insensitive (QDI) circuit properties to significantly harden the architecture with a very low area overhead and a reasonable performance penalty. To validate these techniques, a hardened DES crypto-processor is presented. The countermeasures are evaluated using laser beam fault injection

This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. We address the effects of transient faults in QDI circuits and describe the causes that lead the faults to be memorized into one or more soft errors. Therefore, a refined fault sensitivity criterion is defined for this class of circuits. This methodology enables us to point out the weak parts of a circuit. An analysis tool is implemented to support this evaluation. This tool provides a quantitative study of the fault sensitivity, and enables us to compare the robustness of different architectures of a circuit along the steps of its design flow. The objective of this work is to evaluate the circuits robustness against natural faults (single fault model) and intentional fault injection (multiple faults model).

The paper formally specifies a flow devoted to the design of differential power analysis (DPA) resistant QDI (quasi delay insensitive) asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuit. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture, dedicated to asynchronous logic, and the logic style. The innovative aspects of the architecture are described. Moreover, the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions, thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.

This paper presents a novel programmable logic device (PLD) architecture for implementing and prototyping various styles of clockless or asynchronous circuits. Many classes of asynchronous circuits exist, depending on the timing assumptions that are made at the logical level and the adopted handshake communication protocols. The main objective of this work is to break the dependency between the PLD architecture dedicated to asynchronous logic and the logic style. Indeed, the PLDs dedicated to asynchronous logic are always style-oriented. The innovative aspects of this architecture are described in details. Moreover, the structure is well suited to be adapted with further asynchronous logic evolutions thanks to the architecture genericity. The programmable structure is flexible enough to be used with different logic styles and asynchronous design flows. As an example, a full-adder was implemented in two different styles of logic to demonstrate the PLD architecture flexibility. This work is included in a larger project called TAST, dedicated to the synthesis and the prototyping of multistyle logic asynchronous circuits.

This paper presents an innovating methodology for network-centric globally-asynchronous locally-synchronous (GALS) system prototyping. High-performance multiclock FPGAs are exploited for easy and fast prototyping of GALS systems based of an asynchronous network-on-chip (ANoC) interfacing synchronous standard IP cores. Modularity property of asynchronous circuits is fully exploited to design regular distributed interconnect topologies by the means of basic topology-free building blocks, with a focus and special design effort to solve arbitration and synchronization problems. A case-study is implemented on an up-to-date FPGA which includes two independently clocked processors, memory banks, serial and parallel communication links and an asynchronous DES (data encryption standard) module connected through an asynchronous 5/spl times/5 crossbar. The clock-less modules are implemented using a quasidelay insensitive logic on the FPGA by the means of a dedicated library. Performance figures are reported on the FPGA platform, especially for communication costs, speed and latency of the ANoC.

This paper presents hardening techniques against transient faults for quasi delay insensitive (QDI) circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. We address the effects of transient faults in QDI circuits and describe consequences on the circuit behavior. Three techniques exploiting QDI circuit properties are proposed for hardening. These techniques improve the tolerance to transient faults, and make their detection easier. These techniques are compared in terms of efficiency and cost.

New consumer appliances such as PDA, set top box, GSM/UMTS terminals enable an easy access to the Internet and strongly contribute to the development of e-commerce and m-commerce services. Tens of billion payments are made using cards today, and this is expected to grow in a near future. Smartcard platforms will enable operators and service providers to design and deploy new e- and m-commerce services. This development can only be achieved if a high level of security is guaranteed for the transactions and the customer's information. In this context, smartcard design is very challenging in order to provide the flexibility and the powerfulness required by the applications and services, while at the same time guaranteeing the security of the transactions and the customer's privacy. The goal of the session is to introduce this context and highlights the main challenges the smartcard designers/manufacturers have to face.

Summary form only given. This work presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied from the perspective of making easier and more practical the design of future GALS or GALA SoCs. This work focuses on high-level modeling and delay-insensitive implementations of low-power and reliable fixed and dynamic priority arbiters.

A joint algorithm-architecture analysis leads to a new version of picture segmentation system adapted to multimedia mobile terminal constraints. The asynchronous processors network, with a granularity level of one processor per pixel, based on data flow model, takes less than 10 /spl mu/s to segment a SQCIF $88*72 pixels - image (about 2000 times faster than the classical sequential watershed algorithms). The main originality of the proposed algorithm is only one global synchronization point is needed in order to complete the segmentation transformation, instead of the three (or more) classical points: minima detection, labelization and flooding. Our system tends to cope with multimedia mobile phones constraints, i.e. real time computing circuit, low power. We have simulated and validated this system thanks to "SystemC" library; VHDL synchronous prototyping shows up results accordingly.

For innovative portable products, Systems on Chips (SoCs) containing several processors, memories and specialised modules are obviously required. Performances but also low-power are main issues in the design of such SoCs. Are these low-power SoCs only constructed with low-power processors, memories and logic blocks? If the latter are unavoidable, many other issues are quite important for low-power SoCs, such as the way to synchronise the communications between processors as well as test procedures, online testing, software design and development tools. This paper is a general framework for the design of low-power SoCs, starting from the system level to the architecture level, assuming that the SoC is mainly based on the re-use of low-power processors, memories and logic peripherals. SoCs with many processors, co-processors, memories and peripherals cannot be synchronised with a single master clock, due to larger and larger wire delays in deep submicron technologies. Several clocking schemes have been proposed, such as GALS (Globally Asynchronous Locally Synchronous) but also full asynchronous architectures. This paper will present the advantages and disadvantages of these SoC clocking strategies as well as the impacts on low power. For embedded SoCs containing several processors, one has to write several pieces of software for each processor starting typically from a high-level specification using the C/C++ language. In order to tackle this problem, we propose to first transform the original specification by means of a systematic script of platform-independent source code transformations. That is illustrated by applying global loop transformation techniques to identify asynchronous partitions exhibiting little communication and high locality of access characteristics. In a second stage, we explore multiple-instruction multiple-data (MIMD) mapping onto a given (partly) predefined platform using advanced space-time analysis techniques to maintain low data transfer rates while achieving high system throughput. At the SoC level, accurate cost feedback including high-level power estimation is required. From this essential information, energy trade-offs between application sub-modules can for example be used to refine the solution further. In the case of mapping onto programmable cores with a shared memory hierarchy, a final refinement consists in reorganising the data layout for efficient cache utilisation.

Asynchronous dynamics are introduced for the iterative computation of morphological image filters. We propose a fine-grain asynchronous algorithmic- architectural model that exploits these new possibilities to improve the convergence efficiency of such operators over standard sequential-recursive or parallel-synchronous update modes. We conclude with VLSI design perspectives and show how asynchronism can be exploited both at functional and architectural levels.

The cellular iterative computation model bears upon three broad-ranging application domains: pixel-level image processing, finite-difference approximation of continuum problems (boundary value PDEs) in computational physics, and cellular automata as discrete models of complex locally-interacting systems, aimed at probing their emergent collective properties. The common underlying idea is to compute the global dynamics of a lattice-structured state-space through the iterative propagation of purely local computational dependencies between state-components. A past generation of mesh-connected SIMD array-processors, among which the MPP [Bat 80], CLIP [Pre 84] and CAM [Tof 87] machines, were canonical architectural mappings of this fruitful concept. All were fine-grain synchronous solutions. The new generation of MIMD RISC-based parallel computers that superseded them are essentially coarse-grain and asynchronous; They can simulate a cellular iterative model in a parallel pseudo-synchronous SPMD mode with global coordination mechanisms. A fine-grain asynchronous architectural model departs in a somewhat paradoxical way from these two mainstream approaches. The idea is to match an architecture with a functional concept of a synchronism, specific to cellular relaxation algorithms. As we show in the following, benefits accrue at both levels from this matching.

New asynchronous adder structures with high performances and low cost have been designed. Previous work has only reported the design of carry-save and carry-ripple asynchronous adders. In this study, we have developed new asynchronous adders, Carry Select Adders, Carry Skip Adders, Carry Look Ahead Adders and we compare their potentialities in terms of speed and complexity. First, the functional properties of the conventional asynchronous carry ripple addition scheme are described so as to introduce the capabilities of asynchronous adders and to show how asynchronous operators can be far more efficient than synchronous ones. Then, starting from the well known architectures previously developed to accelerate the addition operation, we first describe their asynchronous equivalents and then show how they can be optimized to fully exploit the functional and electrical dependencies of the computation process with respect to the data.>

Array processors tailored to mesh-based iterative algorithms benefit from shifting to an asynchronous mode. An architecture implementing this functionally asynchronous state-space update with self-timed elementary processors can dispense with the overhead of classical data exchange protocols and offer a flexible hierarchical mapping of the state lattice onto the array. The performance and practical feasibility of this approach are assessed on two application examples: iterative elliptic PDE resolution and image motion estimation using mean field annealing based on Markov random fields models.>

Special-purpose chips based on highly parallel architectures, for possible use in videophone, videoconference, digital TV distribution and HDTV codecs, are considered. Functional interface specifications for a motion estimator to be inserted in a coder system are detailed. The range of possible operative part-kernel architectures is derived, based on formal high-level synthesis methods. A novel implementation using redundant base 2 digital-serial arithmetic is presented, resulting in a compact (70000 transistors) motion estimation VLSI block.>