In theory, the binary phase shift keying (BPSK) modulation requires the least SNR to achieve a given bit error rate. Hence, it is an appealing alternative to implement the SerDes transceivers for die-to-die connections. This paper proposes an all-digital BPSK clock and data recovery (CDR) circuit design that requires neither a PLL nor a reference clock. The proposed CDR consists of a digitally controlled delay lock loop (DCDLL) that delays the BPSK input by T/4, T/2, and T, where T is the symbol period. The CDR manipulates these delayed BPSK signals with digital gates to recover the data first. Then, the recovered data are used to recover the clock. Consequently, the recovered clock always traces the recovered data, allowing the CDR to tolerate considerable input jitters. The all-digital and PLL-free implementation results in a compact and low-power CDR. The experimental results of a test chip fabricated in 90nm CMOS show the BPSK CDR is as tiny as 0.00111mm2. At an effective data rate of 3Gb/s, the BPSK CDR consumes 1.75mW, corresponding to an FoM of 0.58pJ/bit.

This article demonstrates the first functional neuromorphic spiking neural network (SNN) that processes the time-to-first-spike (TTFS) encoded analog spiking signals with the second-order leaky integrate-and-fire (SOLIF) neuron model to achieve superior biological plausibility. An 8-kb SRAM macro is used to implement the synapses of the neurons to enable analog computing in memory (ACIM) operation and produce current-type dendrite signals of the neurons. A novel low-leakage 8T (LL8T) SRAM cell is proposed for implementing the SRAM macro to reduce the read leakage currents on the read bitlines (RBLs) when performing ACIM. Each neuron’s soma is implemented with low-power analog circuits to realize the SOLIF model for processing the dendrite signals and generating the final analog output spikes. No data converters are required in our design by virtue of analog computing’s nature. A test chip implementing the complete output layer of the proposed SNN was fabricated in 90-nm CMOS. The active area is$553.4\ttimes118.6$$\mu$m$^{2}$. The measurement results show that our SNN implementation achieves an average inference latency of 196 ns and an inference accuracy of 81.4%. It consumes 242$\mu$W with an energy efficiency of 4.74 pJ/inference/neuron.

Computing-in-memory (CIM) circuits can energy-efficiently conduct the massive multiply-and-accumulate (MAC) computations required by artificial neural networks (ANNs). However, the CIM’s resolution relies on a fundamental assumption of the CIM design: all memory cells output the same current to their read bitlines (RBLs) given the same read wordline voltage and stored weight bit. In practice, parametric faults due to the devices’ intrinsic process variations may introduce significant errors to the MAC results. This work implements accurate test circuits with a 4kb read-decoupled 8T (RD8T) SRAM macro in 40nm CMOS to investigate the parametric faults caused by the intrinsic process variations. Our measurement results reveal the detailed spatial distribution of the RD8T cells’ output currents and suggest that the CIM accuracy can be improved by calibrating the gain errors of the RBLs.

Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs’ output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only$60~\mu \text{m}$by$1900~\mu \text{m}$which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

A digital background calibration scheme for calibrating the linear, third-order, and fifth-order nonlinear gain errors of the residue amplifiers (RAs) in pipelined ADCs is proposed. By alternating injecting three pseudo-random binary sequences (PRBS) with designated weights to the RA through the sub-DAC, multiple correlations of the nonlinearity-corrected backend ADC's outputs and the injected PRBS signals are computed by digital circuits to estimate the calibration parameters according to the proposed multiple correlation estimation (MCE) method. Three least-mean-square (LMS) loops are used to acquire and track the optimal values of the calibration parameters in background so as to vanish all the errors in the ADC's output. Simulation results of a 14-bit pipelined ADC show the proposed calibration scheme improves the SNDR of the ADC from 31.2 dB to 80.4 dB. The proposed calibration scheme relaxes the design requirements of the RAs, making it well suit the design in advanced technology.

This paper presents a 10-bit SAR ADC operating at a supply voltage (vDD) of 0.225 V and down to 0.2 V for self-sustainable IoT applications. We propose an ultra-low VDD temperature-compensated bias current generator for biasing the comparator against temperature variation to address the temperature-dependent issue of the MOSFETs operating in the subthreshold region. In addition, the design fixes the positive input terminal of the comparator at VDD to bias the input transistor pair of the comparator with a sufficient voltage headroom at such a low VDD. The double-boosted with leakage reduction sampling switch is also proposed to address the severe leakage issue at low sampling rates. A test chip has been fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm2. Measurement results show that at 0.225V, the DNL and INL are within +1.04/-0.66 and +0.97/-1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR with the Nyquist input frequency is 49.8 dB at 450 S/s and 0.225V. The whole ADC totally consumes 0.85 nW at 0.225 V including the circuit leakages. It corresponds to an FoM of 8.0 fJ/conv.-step.

This paper proposes a digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifiers (RAs) in pipelined ADCs. It is based on a novel multiple-correlation estimation (MCE) technique. We define two correction parameters relating to the gain errors of the RA under calibration. By alternately injecting two bi-level pseudo-random signals with designated amplitudes to the RA through the sub-DAC, the desired correction parameters are estimated according to the correlations of the backend ADC's outputs and the injected pseudo-random signals. Two least-mean-square (LMS) loops are adopted to find and to track the optimal values of the correction parameters. Simulation results of a 12-bit pipelined ADC show that the SNDR is improved from 46.4 dB to 73.4 dB with the help of the proposed calibration design. The proposed calibration scheme has the advantages of simple implementation, no restriction on the input signal of the ADC, fast settling, and running in background.

3D-IC is a solution to achieve lower cost and higher performance as the transistor density doubles every 18 months following Moore's law. In recent years, Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the most promising packaging technologies for 3D-IC. In InFO WLCSP, there are some inter-die interconnects. We cannot access these interconnects directly. Therefore, it causes 1-2% test coverage loss. As a result, a built-in self-test (BIST) or other design-for-test (DFT) methodology is necessary to test these interconnects. It is easy to detect open defects and short defects leading to large leakage currents with conventional test methods. However, defects leading to small leakage currents are hard to detect, so we focus on these defects in this work. In this paper, we propose a scheme to measure the small leakage current of these inter-die interconnects. The scheme uses IEEE 1149.1 boundary scan interface. Because boundary scan is a well-adopted standard, the scheme can be integrated into any electronic product easily. Beside four mandatory terminals, we add a reference current input. Users can apply current to compare it with the leakage current. For the input EBSC, two OR gates, a MUX, and a current digitizer are added and it is compared with the conventional BSC. A test chip is implemented to verify our design, which uses the one-polynine-metal (1P9M) 90nm CMOS technology. Measurement results show that the proposed scheme is able to measure the leakage current of the interconnect. In addition, with the dynamic range of 128nA, the current digitizer has 6-bit resolution.

How to efficiently test analog circuits is an open issue because of the lack of widely-accepted analog fault model. This paper studies the impacts of the parametric faults on the transfer function's coefficients of continuous-time and linear-and-time-invariant (LTI) analog circuits from the design's point of view. It is found the parametric faults change the coefficients but not the template of the transfer function (TF) of the circuit under test (CUT). Based on this observation, a test procedure that does not need time-consuming fault simulations is proposed. We show the practical TF coefficients of the CUT can be accurately measured by conducting a simple multi-tone test. In addition, conventional coefficient based tests make pass/fail decisions by checking if any coefficient is outside its pre-computed tolerance box. From the design's point of view, we propose comparing the frequency responses of the measured TF with the design specification to make the final pass/fail decision, the same as what conventional functional tests do.

This work presents a fifth-order OTA-C band-pass filter applying Elliptic low-pass filter and complex filter techniques. The frequency error of the filter due to the effect of process variations is induced by integrating the passive components with the operational transconductance amplifier on chip. A filter circuit with automatic calibration scheme can make the frequency less dependent on process, voltage, and temperature variations. The layout of a test chip is realized using a 0.18 um 1P6M CMOS process. Post-layout simulation demonstrates that the center frequency of the band pass filter is 450 kHz and the dynamic range is 35 dB, It has a total power consumption of 0.14mW.

This work presents a low-voltage indoor energy harvesting using photovoltaic cell. The system doesn't use a dc-dc converter to boost the output voltage so that large external inductors and large capacitors are eliminated. A rechargeable battery is connected to the output for storing the energy. No other external components are needed in the system. A test chip is implemented using a 0.18um CMOS process with a chip area of 0.85×0.85mm2and a power consumption of 272uW. This solar cell provides a voltage of 0.4V~0.55V to the test chip at a minimum illumination of 61~625 Lux. A maximum efficiency of 54% can be obtained when the supply voltage is 0.5V.

The battery management system (BMS) is substantial in diagnosing and controlling the battery modules of emerging electric vehicles (EVs). This paper presents a cost-effective stimulus generator for characterizing the communication channels between the BMS host controller and the battery cells. The characterization data are useful to enhance the reliability of the communication. The proposed stimulus generator only consists of a digital oscillator, a reconfigurable digital Σ-Δ modulator, and an output driver. The all-digital design saves the power and the hardware cost. The digital oscillator provides digital sine waves with well-controlled frequency and amplitude. The proposed reconfigurable digital Σ-Δ modulator allows generating pulse-density-modulated (PDM) bit-streams of particular frequencies that cover the whole band of interest. Hence, the test accuracy is no less than that of conventional sinusoidal waves. Simulation results show that the generated stimuli have very high narrow-band SNRs that is essential to test the frequency responses of the channels.

This paper presents an all-digital phase locked loop (ADPLL) design that features fast frequency locking and a wide tuning range. The all-digital implementation makes the design well suit Gigascale systems in advanced technology. The proposed ADPLL first uses the Regula Falsi method to fast lock the output frequency. Then, a frequency tracking (FT) loop is enabled to stabilize the output frequency against environmental disturbance as conventional PLL does. A test chip has been fabricated in 90 nm CMOS. Measurement results show the proposed ADPLL locks in 7 cycles and provides output frequencies ranging from 460.1 MHz to 6.117 GHz.

This paper presents the design and test of a 14 GSps, four-bit data converter pair in 90 nm CMOS suitable for implementing advanced serial links. The data converter pair consists of a noninterleaved flash analog-to-digital converter (ADC) and a noninterleaved current-steering digital-to-analog converter (DAC). Both the converter designs adopt the wave-pipelining technique to increase the available signal settling time. Through detailed analysis, we show that cascading three active feedback preamplifiers to implement the cores of the comparators in the ADC balances the power budget and the design difficulty when we push the sampling rate to the process limit. Current mode logic gates are used to alleviate the power bouncing issue. To address the difficulty and high cost of testing the extremely high-speed converters, the design embeds the simple design-for-testability circuits cooperating with the on-chip resources to provide two cost-effective test modes. The first test mode cascades the ADC and DAC so that they can be tested at the rated speed without the need of a very high speed logic analyzer. The second test mode enables the eye diagram tests by shuffling the digital outputs of ADC as the inputs of the DAC instead of adopting conventional linear feedback shift register. The experimental results show that the cascaded ADC and DAC pair achieves a 31.0 dBc spurious-free dynamic range and a 25.9 dB signal-to-noise-and-distortion ratio with a 1.11 GHz, -1 dBFS stimulus at 14 GSps. The ADC and DAC consume 214 mW and 85 mW from a 1.0-V supply and occupy 0.1575 mm2and 0.0636 mm2, respectively.

This paper presents the design of a fully-differential low-pass SC biquad filter that allows injecting the parametric and catastrophic faults to it. The design is for the verification of the static linear behavior (SLB) fault model which covers multiple parametric and catastrophic analog faults of sampled data systems. The SLB fault model assumes that a circuit under test (CUT) has a fixed z-domain transfer function (TF) template and the faults alter nothing but the coefficients of the TF. To verify this basic assumption, we first retrieve all coefficients of the TF of the fault-injected biquad from the test results of a three-tone test following the diagnosis-after-test (DAT) procedure. Then, we conduct simulations with other stimulus tones and check if the tested responses fit in those predicted by the retrieved TF. Experimental results verify that the fixed TF template assumption holds for all the faults that we injected.

This paper proposes a static linear behavior (SLB) analog fault model for switched-capacitor (SC) circuits. The SC circuits under test (CUT) are divided into functional macros including the operational amplifiers, the capacitors, and the switches. Each macro has specified design parameters from the design's perspectives. These design parameters constitute a parameter set which determines the practical transfer function of the CUT. The SLB fault model defines that a CUT is faulty if its parameter set results in transfer functions whose frequency responses are out of the design specification. We analyzed the fault effects of the macros and derived their faulty signal-flow graph models with which the faulty transfer function templates of the CUT can be automatically generated. Based on the templates, we proposed a test procedure that can estimate all the parameters in the parameter set so as to test the CUT with multiple faults. Different from conventional single fault assumption, the proposed SLB fault model covers concurrent multiple parametric faults and catastrophic faults. In addition, it does not need to conduct fault simulations before test as conventional analog fault models do. As a result, it addresses the impractically long fault simulation time issue. A fully-differential low-pass SC biquad filter was adopted as an example to demonstrate how to design and use efficient multitone tests to test for the parameter set. The multitone test results acquired during the test procedure also reveal the distortion and noise performance of the CUT though the SLB fault model does not include them.

This paper demonstrates a digitally testable second-order Σ - Δ modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D3T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D3T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ - Δ modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Σ - Δ modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D3T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D3T MUT only consists of 13 switches.

This paper proposes a low-cost output response analyzer (ORA) for the built-in-self-test (BIST) ¿-¿ ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order ¿-¿ modulator and a decimation filter. The CSWF BIST procedure requests an ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and-noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs an accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9 k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.

A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Sigma-Delta modulated bit-stream as its stimulus. The single-bit characteristic ensures that the generated stimulus is nonlinearity free. In addition, the proposed DfDT structure reuses most of the analog components in the test mode and keeps the same loads for the operational amplifiers as if they were in the normal mode. It thereby achieves many advantages including lower cost, higher fault coverage, higher measurement accuracy, and the capability of performing at-speed tests. A second-order Sigma-Delta modulator was designed and fabricated to demonstrate the effectiveness of the DfDT structure. Our experimental results show that the digital test is able to measure a harmonic distortion lower than -106 dBFS. Meanwhile, the dynamic range measured with the digital stimulus is as high as 84.4 dB at an over-sampling ratio of 128. The proposed DfDT scheme can be easily applied to other types of Sigma-Delta modulators, making them also digitally testable.

A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using fast Fourier transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications

A wide bandwidth /spl Sigma/-/spl Delta/ modulation based analog built-in self-test (BIST) system that can diagnose the prototype is presented. It consists of a low-cost design-for-testability (DJT) switched-capacitor filter as the circuit under test (CUT) and a wide bandwidth analog response extractor (ARE) to digitize the analog responses for final DSP analysis. The first stage of the DJT CUT is reconfigured to accept a repetitive /spl Sigma/-/spl Delta/ modulated bit-steam as its stimulus. This DJT technique reuses every original component and thus provides the advantages of lowering the testing cost, increasing the fault coverage as well as the accuracy, and being able to perform the at-speed tests. The ARE is a cascaded 2-1-1-I fifth-order /spl Sigma/-/spl Delta/ modulator equipped with single-bit quantizers to extend the testing bandwidth while retaining moderate tolerance of circuit imperfections. Our measurement results show that this ARE is able to provide a -95 dB spurious free dynamic range over 1 MHz bandwidth when operates at 30 MHz- A multi-tone test is performed to manifest the wide bandwidth and high accuracy of our BIST system. Based on the BIST results, a method of diagnosing the prototype to speed up the time-to-market is also proposed and demonstrated by our BIST system.

Because of their relative robustness to process variation, /spl Sigma/-/spl Delta/ modulation techniques are particularly suitable for VLSI implementations. In this paper, we propose to employ the 1-bit /spl Sigma/-/spl Delta/ modulation ADC (analog-to-digital converter) as the on-chip analog response extractor for analog/mixed-signal BIST (built-in self-test) applications. To validate the idea, a prototype chip with the proposed BIST circuitry has been designed and fabricated. Performance of the BIST circuitry is validated (up to 87 dB dynamic range), and measurement results of the circuit under test (CUT), a 2nd-order low-pass filter, are presented.