A functional (applicative) hardware description language (FHDL), capable of dealing with both the sequential and combinational systems is discussed. The language supports multi-level executable specifications and interpretation of functional specifications as implementations at a given level of primitives. That is, the FHDL specifications are symbolically interpreted to produce structural representations (implementations) of hardware algorithms. The symbolic interpreter presently implements the specification of hardware algorithms at the gate level. The FHDL allows definition of function attributes, such as delay and number of logic level so that the performance characteristics of implementations can be obtained during simulation.