Multi-Stage Noise Shaping (MASH) structures have traditionally supported high-resolution analog-to-digital converters (ADCs) by avoiding instability in high-order single loops. While Sturdy MASH (SMASH) reduces the need for precise analog/digital matching in MASH, it reintroduces stability concerns and distortion in integrators due to larger signal swings. This brief presents a modified SMASH design with an efficient architecture that includes one active integrator and three passive ones. Compared to SMASH, the proposed design achieves a flatter signal transfer function (STF) and lower distortion across a wide band. The quantization noise from the first active integrator is filtered by a passive switched-capacitor filter (SCF) before being fed to a second-order passive noise-shaping (NS) quantizer. The structure can be transformed into a cascade of integrators with feedforward (CIFF) delta-sigma modulator (DSM) that traditionally requires a high-gain block. A fourth-order DSM was designed in 65 nm technology for performance validation and comparison, demonstrating an 89.5 dB SNDR and 92.8 dB dynamic range (DR) within a 500 kHz bandwidth using a 25 MHz clock with OSR =25. The simulated modulator power consumption is$290~\mu $W, yielding a Schreier FOM of 181.9 dB.

High-resolution Discrete-Time ADCs are challenging to drive due to their large input sampling capacitance for thermal noise suppression. Predictive level-shifting, an integrated input driving technique for high-resolution ADCs, enables rail-to-rail linear operation of the input buffer without requiring a higher supply voltage. Using this technique, a predictor implemented as an active analog differentiator is used to preset an analog level shifter so that the input signal is shifted toward the smaller range. In this paper, a digital predictor based on a finite impulse response (FIR) filter is explored to overcome the limitations of the analog predictor, such as process, voltage and temperature (PVT) variations and device saturation. The digital predictor saves 48% power and produces 58% less prediction error compared to its analog counterpart, resulting in a more power-efficient ADC system.

Pseudo-Pseudo-Differential (PPD) architecture can achieve higher power-efficiency with greatly reduced hardware complexity compared with fully- or pseudo-differential architectures. This paper analyzes the operation of PPD delta-sigma ADC, identifying a delay mismatch between the differential loops, which needs special treatment for stability. Resonator and common-mode feedback implementation is explored. Based on the analysis, a 3rd-order PPD delta-sigma ADC is designed for 16-bit accuracy with 100kHz bandwidth at 9.6MS/s sampling speed.

In this paper, a fully passive third order continuoustime (CT) $\Delta\Sigma$ Modulator (DSM) is proposed. By utilizing passive filter, the power cheap DSM still faces poor noise shaping. To improve the performance of this fully passive CTDSM, a Sallen-Key (SK) inserted Q enhancement technique is implemented. The inserted novel SK ensures better noise shaping than the fully passive structure. The proposed DSM is realized in Intel 22nm FinFET process with 0. 9V supply voltage. The passive CTDSM without or with SK (w/oQ enhancement or wQ enhancement) under 5GS/s sampling frequency can achieve 20MHz bandwidth (BW) with SNDR of 63dB, 72dB respectively. FOM values can achieve 55fJ/conv and 21fJ/conv separately.

This paper demonstrates a proposed architecture of multi-stage noise-shaping (MASH) structure with noise shaping successive-approximation (NSSAR) ADC. The proposed intrinsic stable $4^{\mathrm{t}\mathrm{h}}$ order MASH NSSAR ADC can not only take advantage of sharp noise shaping effect but also gain benefits from hardware reuse. With ultra-low oversampling ratio (OSR) the MASH NSSAR is realized in Intel 22nm FinFET process with 0. 9V supply. The noise leakage introduced by the analog and digital filter mismatch will be analyzed and indicates no calibration needed in the proposed MASH under reasonable mismatch range. A PVT stable ring amplifier that can achieve high-speed settling is also proposed in this article. With 100MHz bandwidth (OSR=3) and 50MHz (OSR=6), the topology can achieve 78dB and 85dB SNDR respectively.

A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13$\mu \text{m}$CMOS technology. It achieved 85.1 dB DR, 82.6 dB SNDR and 90.9 dB SFDR within a 2 kHz signal bandwidth with an oversampling ratio OSR = 32. It consumes 40.8$\mu \text{W}$power using a 1.6 V power supply.

One main concern for a continuous-time (CT) multi-stage noise-shaping (MASH) delta sigma (ΔΣ) analog to digital (ADC) is how to make the digital filtering responses match the analog transfer functions of the sub-loop. Since non-ideal factors of CTΔΣ modulator greatly affect analog transfer functions, the accurate estimation of the signal transfer function (STF) and quantization noise transfer function (NTF) affects the final performance of the ΔΣ ADC. In this paper, STF and NTF are simultaneously estimated for CT MASH 0-3-0 ΔΣ ADC with autoregressive and moving-average (ARMA) Model. The proposed method called digital quantization noise leakage reduction algorithm (DQNLRA) could also deal with excess-loop-delay (ELD) and finite gain and bandwidth of op-amp in CTΔΣ modulator.

In this paper, a modified assisted opamp technique is proposed for power saving. The original assisted opamp technique adds assistance circuitry to an integrator that results in significant linearity enhancement. The original method utilizes an analog Gm block and a DAC to provide the assistance needed. The proposed method modifies the assistance circuitry implementation, replacing the Gm block with a digital filter. Transistor level simulations for the first integrator in a continuous-time sigma-delta modulator are used to validate and compare the operation of the proposed technique with the original technique in a 180nm CMOS process. The design example uses a 3rdorder 3bit CIFF modulator with a RZ DAC clocked at 100MHz with an OSR of 32.

A digital subsampling ADC-PLL is simulated using Verilog-A models with ring-amplifier designed in a 65nm CMOS process. The ADC-PLL utilizes a ring-amplifier to relax the design requirements of the ADC. The ring-amplifier provides high open loop gain due to its multi-stage structure while dynamic biasing enables fast settling performance. In the proposed digital subsampling ADC-PLL, the ring-amplifier is operated at a reference frequency of 100MHz and utilizes programmable closed-loop gain from 1 to 100 reducing the quantization noise contribution of the 4-bit flash ADC. The ADC-PLL has an rms jitter of 57.5 fs when only quantization of the ADC and DCO are considered.

This paper presents a method of biasing high gain ring amplifiers with cascoded output stages while retaining the high slew capability of the ring amplifier. The proposed method biases all devices in the output stage using voltages from the previous stage made available by a resistor ladder. Transistor level simulations of a ring amplifier in a 65nm CMOS process are presented showing 80dB settling accuracy within 2ns. The design is used in a switched capacitor amplification configuration with a closed loop gain of 64.

The design of a successive approximation analog-to-digital converter with dynamic redundancy algorithm is proposed. The dynamic redundancy algorithm reduces comparator pre-amplifier activity by completing conversions at an accelerated speed and powering-down early. When bit decisions are restricted to incomplete settling in the DAC and comparator pre-amplifier, errors in the SAR algorithm will occur. The dynamic redundancy algorithm examines the digital word for these errors. Once the algorithm detects errors, the SAR ADC continues the successive approximation algorithm through an auxiliary DAC. The architecture is shown through simulation to reduce comparator pre-amplifier activity down to 28% in comparison to architectures with uniform timing algorithms.

This work presents a design example of how ring amplifier settling differs from a traditional operational amplifier. Ringamps posses dynamic bandwidth characteristics when amplifying discrete-time waveforms. The dynamic bandwidth of ringamps is demonstrated with transistor level simulations in an 180 CMOS process. That experiment shows increased performance when used in low feedback factors compared to operational amplifiers. This work includes a discussion on how the settling performance of ringamps affects system level analog-to-digital converter design.

In this paper, process invariant biasing is proposed for robust operation of ring amplifiers. The ring amplifier is an efficient solution for high accuracy amplification in sub-micron CMOS process. A traditional ring amplifier structure requires an external control voltage, defined as the deadzone voltage, to set the optimum quiescent current at the output stage. Other structures of ring amplifiers use on-chip resistors or current starved inverters to set the deadzone voltage. Since the deadzone voltage is a function of the threshold voltage of transistors in the output stage inverter, ring amplifiers are susceptible to process variations. In this paper, a deadzone regulation circuit is proposed that utilizes a constant current source and a negative feedback loop to regulate the quiescent current of the output stage inverter across process corners. Transistor level simulations are used to validate the operation of the proposed deadzone regulation technique across FF, TT and SS corners in a 65nm CMOS process. The design example uses a current starved inverter based ring amplifier in a switched capacitor amplifier to achieve a closed loop gain of 4 with a settling accuracy of ≤ 0.05% and operated at a sampling rate of 125MHz.

In this paper, passive compensation techniques are proposed: to improve the settling performance of a ring amplifier and to minimize the power consumption of ring amplifiers in high speed applications. The ring amplifier is an efficient solution for high accuracy amplification in sub-micron CMOS process. However, due to the multi stage structure of the ring amplifier, the need for stabilization increases the static power consumption of the amplifier in high speed and high accuracy applications. The proposed technique utilizes LHP zeros obtained from the switches in a switched capacitor feedback network to stabilize the large signal and small signal response of a ring amplifier. Transistor level simulations are used to validate the effect of passive compensation in a 65nm CMOS process. The ring amplifier is designed for an output settling accuracy of ≤0.02% and operated at 150MHz sampling rate. Using the proposed technique, transistor level simulation shows a 72% reduction in static power in comparison to the traditional compensation methods.

This work presents a power saving design method for stochastic flash analog-to-digital converters (ADCs). Stochastic ADCs use the offset noise distribution generated by mismatch to estimate the input signal. By analyzing the characteristic of the noise distribution, some of comparator cells in the stochastic ADC are unused for a given input range. The proposed comparator selection method allows the unused comparators to be powered down without affecting performance of the ADC. A behavioral model of the stochastic ADC is used to simulate and compare the power consumption of the ADC with and without the proposed technique.

This paper presents a new method for ring amplifier biasing to improve their stability while maintaining high slew rate. A multi-path ring amplifier is proposed for switched capacitor applications that allows accurate charge transfer at high speeds. Dynamic biasing improves large signal slewing without affecting residue amplifier settling performance. Stable operation is possible because the auxiliary path turns off dynamically, allowing the main path to be optimized for accuracy. The proposed multi-path amplifier was used in the first stage of a pipelined ADC in 180nm CMOS. Measurements show SNDR, SNR, and SFDR of 73.6 dB, 74.6 dB and 85.5 dB respectively, sampled at 10 MS/s, and consumes 7.68 mW.

A voltage domain correction technique is proposed to mitigate the timing skew errors in time interleaved (TI) analog to digital converters (ADCs). The proposed technique exploits the fact that any timing skew in the sampling edge of a clock results in a corresponding error in sampled voltage that propagates through the ADC. The technique intends to cancel this voltage error by applying a correction voltage at the input sampling network in a TI-ADC. The effectiveness of the technique is demonstrated by using behavioral models of a 14-bit 500MS/s 2 channel TI-pipelined-ADC.

A highly compact continuous-time transimpedance low-pass filter (TILPF) topology is proposed that achieves a low input impedance and a 2nd-order transfer function in a single stage. This is suitable to perform current-to-voltage conversion with a built-in filtering characteristic in a passive mixer based wireless receiver. A 4th-order Butterworth prototype is designed with a cascade of the proposed TILPF and a self-coupled source follower based biquad in a 65nm CMOS. Operating with a 1.3V supply, the filter achieves 30MHz bandwidth while consuming 0.5mA total current. The simulated in-band IIP3 is +17.1dBm, and the average output noise is 14.2nV/√Hz.

This paper presents an in-loop-bandwidth spread-spectrum clock generation by proposing a linear charge-based discrete-time loop filter. The proposed architecture achieves a power efficient (2.29mA/GHz) spread-spectrum modulation scheme based upon a conventional CP-PLL. This work supports a modulation range of +/-2.7 % of a 700 MHz output frequency with the modulation rate in the range of 10 ~ 100 kHz. The measured period rms and peak-to-peak jitters are 2.71 ps, rms and 20.6 ps, pp, respectively. The proposed spread-spectrum clock generator is fabricated in a 180 nm CMOS process and occupies an area of 0.525 mm2.

This paper presents a new dual-slope-based time-interleaved quantizer architecture. Time information between interleaved quantizer channels is utilized to perform time-domain delta modulation. This technique decouples the conversion rate of dual-slope quantizers from their input voltage amplitude without the need for extra timing phases or dedicated hardware.

Time-to-digital converters are an attractive topology for quantization because they rely on mostly digital blocks that benefit from scaling of transistors. Time-to-digital converters inherently need a time-domain input, but the input to analog-to-digital converters is primarily in the voltage-domain. Therefore, a voltage-to-time converter is necessary to use time-to-digital converters in analog-to-digital converters. Previously, circuit modifications have allowed voltage-to-time converters to provide an extra order of quantization noise shaping when used within a delta-sigma analog-to-digital converter. This work proposes another method that allows the voltage-to-time converter to function as an integrator. When combined with previous methods, this allows for an extra two orders of noise shaping to result from the quantizer.

Prior work used least-significant bit first quantization (LSBFQ) to conserve switching energy and comparator bitcycles, but is limited to low activity signals. Furthermore, LSBFQ results in a large bitcycle range in the quantizer. A novel selectable starting bit quantizer (SSBQ) is proposed which starts quantization with neither the MSB nor the LSB, but an intermediate bit chosen for target applications. It is shown that the proposed algorithm reduces bitcycle range in the quantizer compared to LSBFQ, and provides design flexibility for various activity signals. Furthermore, the proposed solution encompasses LSBFQ since it is a specific case of the proposed architecture. For target applications, the proposed solution will save bitcycles in an A/D conversion, as well as switching energy, over the LSBFQ and the merged capacitor switching (MCS) SAR, the most energy-efficient traditional MSB-first SAR.

A ΔΣ ADC using an LSB-first quantizer (LSBFQ) is proposed. LSBFQ are energy-efficient ADCs for processing signals with low activity, and have been proposed as standalone quantizers for sensor and biomedical applications. Since the quantizers in highly oversampled multibit ΔΣ ADC process signals with low average activity, the LSBFQ is an ideal quantizer solution. In order to avoid clocking the LSBFQ at a rate much faster than the rest of the ΔΣ ADC, it is proposed that the quantizer be provided a fixed number of comparison cycles, then be interrupted regardless of whether the conversion has fully completed. This is acceptable because for high oversampling ratios (OSR), the average code change is small and an N-bit conversion can usually be completed in fewer than N comparison cycles. In the rare cases that the quantizer is interrupted early, it injects slightly more quantization noise into the loop filter, which is filtered and shaped with little impact on signal-to-noise and distortion ratio (SNDR). Simulation results demonstrate that for high OSR, an LSBFQ achieves higher resolution and lower capacitor switching energy than a conventional SAR ADC using the same number of comparator bitcycles.

This paper proposes a new continuous-time (CT) MASH delta sigma (ΔΣ) modulator topology in which dual VCO-based quantizers are incorporated. The nonlinearity of both voltage-controlled oscillators (VCOs) caused by their nonlinear voltage-to-frequency (V-to-F) transfer curve are systematically suppressed without any calibration schemes. After the input voltage is directly digitized by a VCO-based quantizer (VCOQ), the residue error, obtained through passive subtraction with a current digital-to-analog converter (DAC), contains its noise-shaped quantization noise as well as the harmonics. This residue error is subsequently processed for fine digitization via a 2nd-order CT ΔΣ modulator where a second VCOQ is incorporated. The harmonics in the first VCOQ's output are fully cancelled at the final digital output, which is collected by summing together the digital bits of the two VCOQs. Behavioral-model simulations demonstrate a 49dB SNDR improvement from the first VCOQ of only 39.3dB SNDR.

A new category of time amplifiers (TA) based on phase accumulation of voltage controlled oscillator (VCO) is proposed. This new technique avoids the use of circuit metastability as conventional TA architectures, and achieves time amplification with digitally controlled and well defined gain. Using the proposed mechanism, two different TA topologies are presented in this paper.

An analysis of the impact of last stage flash in a conventional pipeline ADC is performed in this paper. The performance of a pipeline ADC can be altered significantly by calibrating the comparators in the back-end flash. Also, realizing that the input to the back-end flash (in a pipeline ADC) is not uniformly distributed, this paper proposes alternative back-end flash references to improve the overall performance of the ADC. An analysis of the performance of the pipeline with large offsets in the MDAC stages is also presented in this paper.

The early reset merged capacitor switching algorithm (EMCS) is proposed as an energy reducing switching technique for a binary weighted, capacitive successive approximation (SAR) analog to digital converter (ADC). The method uses the merged capacitor switching (MCS) architecture and optimizes the use of the VCMlevel during the SAR conversion. This algorithm can reduce switching power by over 12% with no additional DAC driver activity when compared to the MCS scheme. The MCS and EMCS approaches are analyzed mathematically and the EMCS energy consumption is shown to be lower than or equal to that of the MCS technique for every digital code. Static linearity improvements for this structure are also shown with the integral non-linearity (INL) reducing by a factor of two due to the utilization of the MCS three level DAC. The EMCS implementation methodology is also described.

The relation between opamp noise and the size of the level shifting capacitor in correlated level-shifting (CLS) architectures is explored. Analysis is performed for a Split-CLS switched capacitor amplification circuit, and many of the conclusions in this paper are applicable to more general CLS architectures as well. A theoretical model for noise is developed and shown to be in good agreement with simulation. It is found that for practical design values, the size of the level-shifting capacitor only weakly influences noise performance.

In this paper, the Correlated Jitter Sampling (CJS) technique, which alleviates the jitter induced error from the time reference in pipelined Time-to-Digital Converter (TDC), is proposed. The auxiliary pipelined TDC is employed to remove the jitter induced error of the main pipelined TDC in the CJS technique. A 12b pipelined TDC adopting the CJS technique in the 1sttime quantization stage is simulated to validate the proposed technique. Simulation results show that the TDC can achieve a flat SNDR performance of 70dB regardless of the jitter from time reference up to 25% jitter of 1TLSBin reference clock, which is the maximum error allowed within a designed redundancy range of the pipelined TDC.

This paper demonstrates Class-A+ amplifier as an alternative to Class-A amplifier for discrete-time signal processing circuits. Class-A+ amplifier uses cross-coupled latches during the amplification phase at the output to improve settling accuracy compared to Class-A amplifier. The positive feedback latch is reset to fixed bias voltages of the Class-A output stage during the reset-phase. This dynamic compensation technique for realizing stable amplifier enables power and area savings with improved settling accuracy and THD performance. Simulation results show 30% reduction in overall power consumption, 50% reduction in the size of output stage and 10 dB improvement in settling accuracy compared to conventional Class-A amplifier with similar worst case settling time.

An optimized memory structure, Binary Access Memory (BAM), is presented for successive approximation applications that employ an error correction lookup table. Unlike true random-access memory, the probability of different codes occurring in a binary successive approximation access pattern is not uniformly distributed. BAM exploits this fact in several ways to reduce the number of sub-block switches, the average and worst-case access latency, and power consumption compared to a conventional SRAM lookup table. A simple technique for using BAM in an asynchronous successive approximation design is also presented.

A precise return-to-zero current steering DAC is presented. This architecture uses a scaled switched-capacitor replica and a comparator to integrate the current over time, resulting in an accurate pulse. Without significant increase in the pulse height, the generated pulse can have its minimal value at the end of the DAC phase, hence minimizing the clock jitter effect. The proposed DAC can be used in continuous-time delta-sigma modulators to achieve high accuracy even in presence of the clock jitter. Simulation results are provided to prove the efficiency of this structure.

A single-loop delta-sigma modulator based on path-coupling and double-sampling is proposed. This modulator employs a noise-shaped integrating quantizer which by itself increases the order of noise shaping by one. The integrating quantizer used in this structure holds its quantization error at the end of the evaluation phase, and hence this voltage is available in purely analog form and eliminates the need for extra DACs. This enables to utilize local path-coupling which adds another order of noise shaping. A third order example is provided and simulated to demonstrate the efficiency of this structure.

This paper presents a pseudo-differential zero-crossing-based circuit topology that achieves differential error suppression. The nature of the charging errors in different zero-crossing-based circuit topologies is explored and the benefits of the proposed topology are discussed. Simulation results provided confirm the differential error suppression in the proposed scheme.

An Interstage Correlated Double Sampling technique is proposed. This new technique avoids the additional thermal noise penalty and the overall feedback factor degradation introduced by the conventional correlated double sampling techniques. In the proposed architecture, a two-stage amplifier is employed and the correlated double sampling is applied to the input of the second gain-stage. The superior noise performance and the gain enhancement of the proposed architecture to the conventional CDS technique is demonstrated in this paper.

This paper presents a technique for automated design and optimization of low-noise oscillators. A sensitivity analysis for oscillators guides the reduction of oscillator noise intensities and improvement of oscillator's immunity to noise. A design-oriented approach to circuit analysis efficiently handles design constraints and reduces the dimensionality of the optimization problem. The perturbation projection vector based phase noise computation makes the proposed optimization technique general and applicable to all types of oscillators, independent of circuit topology. Several examples illustrate the benefits of the new optimization approach.

A design-oriented periodic steady-state analysis is presented in this paper. The new analysis finds the values of circuit parameters that result in a desired circuit performance specified by a set of equality constraints. This is done by including the design equality constraints and the circuit parameters directly in the steady-state analysis as additional equations and unknowns. A time-domain finite difference method and the numerical implementation for the proposed analysis are described. Several examples demonstrate that the new analysis accurately and efficiently tunes circuit parameters that conform to a wide range of design specifications.

This paper shows how the relative size of components can be used to increase matching performance - saving orders of magnitude in component area. The relative size information can be found by ordering the elements from smallest to largest. A circuit to do this is described. Properties of ordered devices are summarized. Improvements are quantified for simple feedback circuits and matched devices constructed from ordered sub- elements. The INL of a 17-level D/A converter is simulated, and the methods are shown to increase linearity by 5 bits.

An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards high order multi-loop modulators are discussed and a new multi-loop modulator is presented. This modulator benefits from a MASH architecture in the final loop to preserve stability, while the main loop benefits from relaxed circuit building blocks of the SMASH structure. Extensive simulation results are provided to prove the efficiency of this structure.

A new delta-sigma Analog-to-Digital Converter (ADC) is presented in this paper. A two-step pipeline ADC is used as the quantizer of this delta-sigma modulator to reduce the quantization noise at the output of the modulator. The proposed structure relaxes the output swing and gain requirements of the integrators. In addition, the front-end DAC of the proposed modulator is simplified. Simulation results verify the effectiveness of the proposed architecture.

A new oscillator sensitivity analysis that predicts the impact of parameter variations of a VCO in a PLL is presented in this paper. Sensitivities of an oscillator's steady-state performance to design, process, or environmental parameter variations can be accurately and efficiently computed with the proposed analysis.

This paper presents an analysis for calculating sensitivities of an oscillator's periodic steady state and perturbation projection vector to design, process, or environmental parameters. A general continuous-time formulation and time-domain numerical methods are described. The applications of the oscillator sensitivity analysis in design optimization, macromodeling, as well as in analyzing the impact of process variations are demonstrated through examples.

This paper presents a generalized formulation of the periodic steady-state analysis for oscillators. The new formulation finds the value of a circuit parameter that results in a desired oscillation frequency for the circuit. Numerical methods based on the time-domain finite difference and shooting methods, and the frequency-domain harmonic balance method are described. Comparisons with search-based methods demonstrate the efficacy of the new approach.

This paper presents an analysis for calculating sensitivities of an oscillator’s periodic steady-state and perturbation projection vector to design, process, or environmental parameters. A general continuous- time formulation is described. Applications of the oscillator sensitivity analysis in design optimization and macromodeling are demonstrated through examples.

This paper introduces series/parallel and parallel/series composite resistor topologies. These topologies allow one to design a temperature coefficient that is insensitive to process variations, unlike the traditional simple series and simple parallel composite resistors. Formulas and normalized circuits are provided. Four zero-temperature coefficient resistors are simulated, and methods for picking the best topology are discussed.

This paper presents a high-speed digital feedforward delta-sigma modulator which relaxes timing requirement for the dynamic element matching (DEM) algorithm. By making the main digital to analog converter (DAC) process a small part of the input signal, the distortion from the DAC is suppressed. The proposed method allows eliminating the DEM circuitry in the critical data path for high-speed applications, thus achieving high-resolution without augmenting considerable silicon area. Analysis and simulation results verify the effectiveness of the proposed method.

An enhanced version of Sturdy MASH (SMASH) (Maghari et al., 2006) delta-sigma modulator is proposed. This structure takes advantage of the well-known stability of the MASH structure while greatly reducing its sensitivity to imperfect circuit blocks. Furthermore, no digital noise cancellation filters are needed. Hence there is no matching requirement for the analog and digital paths. With the proposed enhancement in noise shaping, the first and second stage quantization noise experience different (thus mixed) orders of noise shaping, and the accuracy of this modulator is comparable of that of the MASH structure. Simulations results and mathematical analysis demonstrate the effectiveness of this structure.

In this paper a modification of the time-domain periodic steady-state analysis for oscillators is presented. The proposed analysis finds the value of a circuit parameter that results in the circuit oscillating at a desired frequency. This analysis is based on the steady-state analysis for voltage and current controlled oscillators, i.e., replacing the oscillation period by a circuit parameter in the list of unknowns. A generalized formulation that can handle a control voltage or current, as well as any frequency-tuning circuit parameter, such as a tank capacitor or device geometry is developed in this paper.

The goal of this paper is to provide an intuitive approach to switch sizing in SC circuits, focusing primarily on the MDAC of a pipelined ADC. Theory and simulation show that properly choosing the switch resistances to create a critically damped system can reduce the settling time of the circuit.

A method to generate stable transconductance (g/sub m/) without using precise external components is presented. The off-chip resistor in a conventional constant-g/sub m/ bias circuit is replaced with a variable on-chip resistor. A MOSFET biased in triode region is used as a variable resistor. The resistance of the MOSFET is tuned by a background tuning scheme to achieve the stable transconductance that is immune to process, voltage and temperature variation. The transconductance generated by the constant-g/sub m/ bias circuit designed in 0.18/spl mu/m CMOS process with 1.5F supply displays less than 1% variation for a 20% change in power supply voltage and less than /spl plusmn/1.5% variation for a 60/spl deg/C change in temperature. The whole circuit draws approximately 850/spl mu/A from a supply.

LC-tuned voltage controlled oscillators (LC VCOs) are widely used in high performance phase locked loops (PLLs) and frequency synthesizers due to their high spectral purity. The oscillation frequency of an LC VCO is commonly assumed to be the resonant frequency of the LC tank. However, this is not accurate as shown in this paper. The oscillation frequency is also affected by the bias current. By applying our analysis to the Hegazi and Abidi's LC VCO, we propose a new digital trimming technique which can compensate for process variations and improve the phase noise performance

This paper introduces a new architecture for sensor interface circuits using a delta-sigma modulator. The three-level force feedback allows the use of a digital compensator to stabilize the loop. A 3rd-order delta-sigma structure shapes the opamp noise and allows two-chip implementation with high loop gain at low frequencies.

Cascaded delta-sigma (MASH) converters offer a good compromise between high accuracy, robust stability and speed. However, they are very sensitive to analog circuit imperfections. This paper presents an improved adaptive on-line digital compensation of these errors. Behavioral and circuit-level simulations have confirmed an achievable 13 bit performance and 6 MHz bandwidth for the proposed ADC.

In this paper we present a new circuit design for a 2.4 GHz CMOS direct conversion mixer incorporating adaptive offset cancellation. The basic circuit structure is that of a Gilbert cell mixer. Offsets are cancelled by dynamically varying the bias on the loads, which are designed to provide constant impedance independent of the load cancellation current. The bias control is regulated via an adaptive dual-loop (gear-shifting) algorithm. Performance is good when canceling offsets of any realistic magnitude. The mixer has a gain of 6.4 dB, IIP3 of 17 dBm and noise figure of 17 dB.

This paper describes a background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analog converter. It can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed.

Novel common-mode feedback circuits are proposed for use in pseudo-differential switched-capacitor circuits. They can be implemented by incorporating just four additional capacitors (and switches) for an integrator, and only two additional capacitors for a residue gain amplifier. The circuits are applicable to very low-voltage switched-capacitor stages realized in submicron low-voltage CMOS processes.

An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme together with the correlated double sampling (CDS) technique, the virtually error-free and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in applications which require low-cost medium-speed and high-resolution A/D conversion.