We present an LC-based hybrid sub-sampling phase-locked loop (PLL). A novel tri-state integral path is applied to reduce the loop filter (LF) area and eliminate ripples on the control signals. The effectiveness of the proposed technique is compared with type-II hybrid PLL and PLL using delta-sigma modulator. The 24.6-29.6GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 44fs and -254.8dB FOM and consumes power of 17mW from a 0.9/0.95V supply.

This article introduces a cascaded sliding-block decision feedback equalizer (SB-DFE) that equalizes multiple precursor and postcursor intersymbol interference (ISI). The paper also presents an enhanced statistical analysis for the DFE in the presence of residual ISI and additive white Gaussian noise (AWGN), along with generalized expressions for the probability and expected length of DFE burst errors. In addition, the statistical analysis is extended to the conventional SB-DFE and our proposed cascaded SB-DFE to accurately estimate their equalization capability, latency, and steady-state bit error rate (BER). The simulation results reveal that the cascaded SB-DFE provides as low BER as the mininum mean-squared error - DFE (MMSE-DFE) with substantially lower latency and hardware overhead.

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.

We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology. LAYGO supports rapid generation by placing customized templates on process-specific placement grids, thereby encapsulating the design rules and process-specific structures. The templates can be located based on their relative positional information, which further enhances the description capability and portability. Interconnecting wires are routed on the grids for design rule abstractions, with additional customizations and support for multi-patterning. The functions for the on-grid placement and routing use advanced indexing and slicing with multi-dimensional object containers to improve the description and parameterization capabilities. Multiple TI-SAR ADC layouts are generated using LAYGO in 28-16 nm CMOS technologies. One instance is fabricated in a 16 nm CMOS FinFET process and measured, achieving a 38.2 dB signal-to-noise-and-distortion ratio (SNDR) at 7 GS/s after digital calibration and consuming 45.2 mW. Owing to its high customization capability, the design achieved the highest sampling rate (7 GS/s) among the generated ADCs.

Printed Circuit Board (PCB) design tools are critical in helping users build non-trivial electronics devices. While recent work recognizes deficiencies with current tools and explores novel methods, little has been done to understand modern designers and their needs. To gain better insight into their practices, we interview fifteen electronics designers of a variety of backgrounds. Our open-ended, semi-structured interviews examine both overarching design flows and details of individual steps. One major finding was that most creative engineering work happens during system architecture, yet current tools operate at lower abstraction levels and create significant tedious work for designers. From that insight, we conceptualize abstractions and primitives for higher-level tools and elicit feedback from our participants on clickthrough mockups of design flows through an example project. We close with our observation on opportunities for improving board design tools and discuss generalizability of our findings beyond the electronics domain.

We describe our experience developing and promoting a set of open-source tools and IP over the last 9 years, including the Chisel hardware construction language, the Rocket Chip SoC generator, and the BAG analog layout generator.

This review focuses on recent directions stemming from work by the authors and collaborators in the emerging field of neurotechnology. Neurotechnology has the potential to provide a greater understanding of the structure and function of the complex neural circuits in the brain, as well as impacting the field of brain-machine interfaces (BMI). We envision ultralow-power wireless neural interface systems that are life-lasting, fully integrated, and that supports bidirectional data flow with high bandwidth. Moreover, we believe in the importance of building neural interface technology that is truly tetherless, has a very small recording footprint, and little to no mechanical coupling between the sensor and the external world. We believe these developments will impact both neuroscience and neurology, revealing fundamental insight about how the nervous system functions in health and disease.

Many-element antenna arrays, used for multi-user MIMO, are expected to be one of the cornerstone technologies for 5G wireless systems. Large arrays also offer the opportunity to average out some of the transceivers' analog imperfections, potentially enabling a lower-power implementation. In this paper we study the effect of local oscillator phase noise on beamforming MU-MIMO-OFDM systems. We show that the array does average out uncorrelated phase noise at each element. Exploiting this, we propose scaling the per-element phase noise specification proportionally to the array size, thereby maintaining constant array-level performance with lower power consumption. However, if the phase noise is entirely uncorrelated, this scaling causes a substantial degradation in the recovered signal energy. If, instead, some correlated low-frequency phase noise is introduced at each element, we show that phase noise scaling incurs no performance loss. In fact, under these conditions, a single, global pilot tracking loop can replace carrier recovery at each element. Additionally, this level of phase noise correlation eliminates the phase noise-induced channel aging effect. This type of correlation can be achieved by distributing a common reference and optimizing the bandwidth of the PLL.

Large arrays of radios have been exploited for beamforming and null steering in both radar and communication applications, but cost and form factor limitations have precluded their use in commercial systems. This paper discusses how to build arrays that enable multiuser massive multiple-input-multiple-output (MIMO) and aggressive spatial multiplexing with many users sharing the same spectrum. The focus of the paper is the energy- and cost-efficient realization of these arrays in order to enable new applications. Distributed algorithms for beamforming are proposed, and the optimum array size is considered as a function of the performance of the receiver, transmitter, frequency synthesizer, and signal distribution within the array. The effects of errors such as phase noise and synchronization skew across the array are analyzed. The paper discusses both RF frequencies below 10 GHz, where fully digital techniques are preferred, and operation at millimeter (mm)-wave bands where a combination of digital and analog techniques are needed to keep cost and power low.

Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency.

We introduce BAG, the Berkeley Analog Generator, an integrated framework for the development of generators of Analog and Mixed Signal (AMS) circuits. Such generators are parameterized design procedures that produce sized schematics and correct layouts optimized to meet a set of input specifications. BAG extends previous work by implementing interfaces to integrate all steps of the design flow into a single environment and by providing helper classes - both at the schematic and layout level - to aid the designer in developing truly parameterized and technology-independent circuit generators. This simplifies the codification of common tasks including technology characterization, schematic and testbench translation, simulator interfacing, physical verification and extraction, and parameterized layout creation for common styles of layout. We believe that this approach will foster design reuse, ease technology migration, and shorten time-to-market, while remaining close to the classical design flow to ease adoption. We have used BAG to design generators for several circuits, including a Voltage Controlled Oscillator (VCO) and a Switched-Capacitor (SC) voltage regulator in a CMOS 65nm process. We also present results from automatic migration of our designs to a 40nm process.

Power density has grown to be the dominant challenge for continued complementary metal–oxide–semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process technology, this has led to renewed interest in mechanical computing for ultralow-power integrated circuit (IC) applications. This paper provides a brief history of mechanical computing followed by an overview of the various types of micromechanical switches, with particular emphasis on electromechanical relays since they are among the most promising for IC applications. Relay reliability and process integration challenges are discussed. Demonstrations of functional relay logic circuits are then presented, and relay scaling for improved device density and performance is described. Finally, the energy efficiency benefit of a scaled relay technology versus a CMOS technology with comparable minimum dimensions is assessed.

To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nano-electro-mechanical (NEM) relays. A dynamical Verilog-A model of the NEM relay is described and correlated to device measurements. Using this model we explore NEM relay design strategies for digital logic and I/O that can significantly improve the energy efficiency of the whole VLSI system. By exploiting the low effective threshold voltage and zero leakage achievable with these relays, we show that NEM relay-based adders can achieve an order of magnitude or more improvement in energy efficiency over CMOS adders with ns-range delays and with no area penalty. By applying parallelism, this improvement in energy-efficiency can be achieved at higher throughputs as well, at the cost of increased area. Similar improvements in high-speed I/O energy are also predicted by making use of the relays to implement highly energy-efficient digital-to-analog and analog-to-digital converters.

Intersymbol interference (ISI) due to modal dispersion is the dominant limitation to the bit rate-distance product in multimode fiber-optic communication systems. If the light launched into the fiber excites only the desired principal modes, modal dispersion can be eliminated. We can achieve this by using spatial light modulators (SLMs) to perform adaptive spatial filtering on the electric fields of the light. In this paper, we develop an optimization framework for setting the SLMs to obtain an upper bound on the achievable performance and develop heuristics that nearly reach this upper bound Using this framework, we show that both a sophisticated semidefinite programming-based algorithm and a simple adaptive algorithm achieve performance close to the upper bound. Performance and system complexity tradeoff curves are constructed, showing that a 20/spl times/20 array of SLM pixels with binary phase control performs within 15% of more complex implementations. Finally, we extend the framework and present preliminary results showing the promise of further increases in the capabilities of multimode fiber by using the fiber as a multiple-input multiple-output (MIMO) transmission medium.