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A. C. Rajeev

dblp:59/559 · DBLP profile ↗
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8ranked-venue papers
3as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-authorSoftware engineering, systems software and programming languages · 4 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 38% Software testing · 32% Requirements engineering and software design · 19%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Embedded and real-time systems · 33%

Topics — the 9 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
code generation
0.212014
Translation Validation for Stateflow to C · DAC 2014
Requirements engineering and software design › model-driven engineering
model-driven development
0.212014
Translation Validation for Stateflow to C · DAC 2014
Compilers and program optimization › verified compilation
translation validation
0.212014
Translation Validation for Stateflow to C · DAC 2014
Software testing
black-box testing
0.112010
CoGenTe: a tool for code generator testing · ASE 2010
Software testing › compiler testing
code generator testing
0.112010
CoGenTe: a tool for code generator testing · ASE 2010
Software testing
test adequacy
0.112010
CoGenTe: a tool for code generator testing · ASE 2010
Embedded and real-time systems › real-time synchronization
clock drift
0.112008
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts · DAC 2008
Electronic design automation › timing analysis
end-to-end latency analysis
0.112008
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts · DAC 2008
Electronic design automation › hardware verification and test
formal verification
0.112008
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts · DAC 2008

Methods — techniques the papers use, named apart from their topics

timed automata · 0.1model checking · 0.1
YearPublicationVenuePosition
2014 Translation Validation for Stateflow to C
abstract
Code generators play a critical role in the Model Based Development of complex software systems. This is particularly true in the automotive domain, where the code auto-generated from Simulink/Stateflow models is directly flashed onto embedded controllers. Testing based approaches are popular for validating the translation of models to code. However, these approaches cannot guarantee the absence of bugs introduced during translation.
Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh 0002
DAC2
2012 Verifying timing synchronization constraints in distributed embedded architectures
abstract
Correct functioning of automotive embedded controllers requires hard real-time constraints on a number of system parameters. To avoid costly design iterations, these timing constraints should be verified during the design stage itself. In this paper, we describe a formal verification technique for a class of timing constraints called timing synchronization constraints in the recent adaptation of AUTOSAR standard (WPII-1.2 Timing Subgroup, Release 4.0). These constraints require, unlike the well studied end-to-end latency constraint, simultaneous analysis of multiple task/message chains or multiple data items traversing through a task/message chain. We show that they can be analyzed by model-checking with finite-state monitors. We also demonstrate this method on a case-study from the automotive domain.
A. C. Rajeev, Swarup Mohalik, S. Ramesh 0002
DATE1
2010 Schedulability and end-to-end latency in distributed ECU networks: formal modeling and precise estimation
abstract
Embedded control systems in automobiles are typically implemented by a set of tasks deployed on multiple Electronic Control Units (ECUs) communicating via one or more buses like CAN or FlexRay. In the case of safety-critical systems, there are hard real-time bounds on the (i) response times of tasks/messages, and (ii) end-to-end latencies of certain task/message chains. These depend on various factors like the number of tasks (and messages) involved in the processing (and communication) sequence, parameters of these tasks/messages, scheduling policies, communication protocols, clock drifts, etc. Moreover, since the data transfer among tasks/messages is typically via asynchronous buffers that are overwritable and sticky, multiple semantics are possible for end-to-end latency. Hence, precise estimation of response times and end-to-end latencies in embedded systems is a non-trivial problem.
A. C. Rajeev, Swarup Mohalik, Manoj G. Dixit, Devesh B. Chokshi, S. Ramesh 0002
EMSOFT1
2010 CoGenTe: a tool for code generator testing
abstract
We present the CoGenTe tool for automated black-box testing of code generators. A code generator is a program that takes a model in a high-level modeling language as input, and outputs a program that captures the behaviour of the model. Thus, a code generator's input and output are complex objects having not just syntactic structure but execution semantics, too. Hence, traditional test generation methods that take only syntax into account are not effective in testing code generators. CoGenTe amends this by incorporating various coverage criteria over semantics. This enables it to generate test-cases with a higher potential of revealing subtle semantic errors in code generators. CoGenTe has uncovered such issues in widely used real-life code generators: (i) lexical analyzer generators Flex and JFlex, and (ii) The MathWorks' simulator/code generator for Stateflow.
A. C. Rajeev, Prahladavaradan Sampath, K. C. Shashidhar, S. Ramesh 0002
ASE1
2008 Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
abstract
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In this paper we give a formal definition of end-to-end latency, and use this as the basis for checking whether a stipulated deadline is violated within a bounded time. For unbounded verification, we model the system as a set of communicating Timed Automata, and perform reachability analysis. The proposed method takes into account the drift of clocks which is shown to affect the latency appreciably. The method has been tested on a medium sized automotive example.
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh 0002, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang
DAC2
2008 Behaviour Directed Testing of Auto-code Generators
abstract
This paper addresses the problem of testing auto-code generators. Auto-code generators take as input a model in certain modeling language, and produce as output a program that captures the execution semantics of the input-model. We focus on the problem of test specification for the purpose of automatically generating a test-suite. We propose a novel technique for test specification based on the execution behavior of models. We also propose an algorithm that uses such a behavioral test specification for directing test-case generation towards very specific behavioral patterns that we would like to exercise. We have implemented this technique, and have applied it for generating test-cases for a Stateflow auto-code generator.
Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh 0002, K. C. Shashidhar
SEFM2
2007 Testing Model-Processing Tools for Embedded Systems
abstract
Model-based development is increasingly becoming the method of choice for developing embedded systems for applications in automotive and aerospace industries. It relies on tool-suites consisting of a variety of model-processing tools like simulators, model-translators and code-generators. The correctness of these tools used in the development process is a key requirement for safety critical applications. This paper proposes a novel testing methodology for the rigorous verification of model processing tools. The proposed methodology takes as input the syntactic and semantic meta-model of a modeling language, expressed in the form of inference rules. Using a coverage criteria over this meta-model, it generates test-models, and test-inputs for these test-models. Apart from testing the syntactic aspects of the translation, our method aims at testing subtle semantic interactions of the modeling language that are potentially mistranslated by the model-processing tools. We illustrate the methodology with a simple prototypical process calculus. We also report on the experiments carried out with Stateflow, a variant of hierarchical state-machines implemented in the Matlab/Simulink tool-suite
Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh 0002, K. C. Shashidhar
IEEE Real-Time and Embedded Technology and Applications Symposium2
2007 How to Test Program Generators? A Case Study using flex
abstract
We address the problem of rigorous testing of program generators. Program generators are software that take as input a model in a certain modeling language, and produce as output a program that captures the execution semantics of the input-model. In this sense, program generators are also programs and, at first sight, the traditional techniques for testing programs ought to be applicable to program generators as well. However, the rich semantic structure of the inputs and outputs of program generators poses unique challenges that have so far not been addressed sufficiently in the testing literature. We present a novel automatic test-case generation method for testing program generators. It is based on both syntax and semantics of the modeling language, and can uncover subtle semantic errors in the program generator. We demonstrate our method on flex, a prototypical lexical analyzer generator.
Prahladavaradan Sampath, A. C. Rajeev, K. C. Shashidhar, S. Ramesh 0002
SEFM2