Motion estimation plays an important role in video compression to remove temporal redundancies between successive frames. It is also useful in aiding detection of moving objects. Full-search block-matching (FSBM) is the most preferred algorithm for motion estimation. Frame-level pipelined FSBM architectures have advantages over block-level pipelined architectures in their simpler control and reduced number of memory accesses. In this paper, a frame-level pipelined FSBM motion estimation array processor for large search range p = qN is presented where q/spl ges/ 1/2 and N/spl times/N is the block size.

This paper presents a fast algorithm for computing the Hough transform on SIMD hypercube architectures. For an image with N/spl times/N pixels and n quantized /spl theta/ values, our algorithm computes the Hough transform in O(logN) time on a hypercube of size N/spl times/N/spl times/n. An efficient algorithm for large Hough transform problems on a smaller fixed-size hypercube is also given. On a hypercube of size M/spl times/M/spl times/m, the time complexity is O(L/sup 2/l)=O(N/sup 2/n/M/sup 2/m) where L=N/M and l=n/m. Thus, the algorithm for large problems produces linear speed-up and optimal efficiency.

The singular value decomposition (SVD) has many real-time applications. Recently, there has been much interest in developing efficient methods to compute SVD in parallel machines. This paper presents an efficient method for computing SVD in a cube connected SIMD (single instruction stream - multiple data stream) parallel computer. The method is based on a one-sided orthogonalization algorithm due to Hestenes. In a cube connected SIMD with n/2 processors, the SVD of an m by n matrix requires a computation time of O(mn) per sweep. Although the time complexity (excluding communication time) is the same as that of the best known SVD method on linearly connected SIMD, the communication time is much smaller because the amount of data moved among the nodes is only about one half. The SVD of large matrices on a fixed size system is also discussed.

Two critical factors affecting the utility of a VLSI processor array are 1) the versatility of the array, and 2) the size problem due to I/O constraints.In this paper we present a feedback systolic array system for matrix computations which, in addition to being able to produce high throughput, has improved utility.The array system can solve many matrix problems containing arbitrarily large matrices.It can also process sparse matrices efficiently by skipping blocks of zeros.

A method for realization of fail-safe sequential machines, using a class of separable codes called Berger codes in the state assignment, has been presented. The separability property is desirable in certain applications. Both on-set and off-set realizations are used for the next-state functions and this has the advantage over the methods using only on-set realization in that the checker is simpler. Realization of the output circuit is also considered.

Several synthesis methods for fail-safe asynchronous sequential machines have been reported recently. All of these methods solve the race problem by using noncritical race state assignments. This approach generally results in large number of state variables, relatively complicated design, and the limitation of single-input change.

A synthesis method for multiple-input change asynchronous sequential machines is proposed. The method is based on the self-synchronization principle. The internal states are realized with edge-sensitive flip-flops which are triggered selectively. The new concept of selective triggering or controlled excitation results in considerable saving in logic and more flexible design. The state assignment is arbitrary, and the number of state variables required can be made absolutely minimum. A detailed comparison of the speed of operation is made with one of the well-known methods of realization. It is found that our realization is, in general, as fast, and sometimes could be even faster.