Recent increases in VLSI processor speed and transistor density have not been matched by a proportionate increase in the number of I/O pins used to communicate information on and off chip. Since the number of I/O pins is limited by packaging technology and switching constraints, this trend is likely to continue, and I/O bandwidth will become the primary VLSI system performance bottleneck. This paper analyzes the potential of address and data stream coding in order to reduce bandwidth requirements

Simulations indicate a simple modification of existing virtual memory hardware can significantly reduce the number of pins required to transmit address information from processor to off-chip memory. This modification consists of partitioning a TLB so that virtual page numbers are stored in a cache on the processor and corresponding real page numbers are sotred in registers at the memory, making it possible to transmit a small register index instead of the entire real page number.

This paper develops shared memory algorithms for asynchronous processor systems that require the same expected work as the best PRAM algorithms. These algorithms operate efficiently under general asynchronous processor behavior (where individual processor speeds are allowed to vary widely over time). This paper achieves these results by employing a methodology that uses randomization to schedule subtasks of a parallel program. The resulting algorithms allow processors to (i) have arbitrary asynchronous behavior, (ii) have fail-stop errors, (iii) join a computation at any time, and (iv) have no unique identifiers. This paper develops a performance metric for asynchronous parallel computations, called work, which is the total number of instructions (including busy-waiting instructions) performed by a collection of parallel processors during a computation. The main result is to compute any associative function of n variables with $O(n)$ expected work, using up to $n/\log n\log^* n$ asynchronous processors, and with $O(n\log n)$ expected work using up to n processors. These results provide a synchronization primitive that can be used to transform any PRAM program into an asynchronous PRAM program.

Whenaddress reference degrees of spatial and temporal higher order address lines carry streams exhibit high locality, many of the redundant information.By caching the higher order portions of address references in a set of dynamically allocated base registers, it becomes possible to transmit small register indices between the processor and memory instead of the high order address bits themselves.Trace driven simulations indicate that this technique can significantly reduce processor-to-memory address bus width without an appreciable loss in performance, fhereby increasing available processor bandwidth.Our resulfs imply that as much as 25% of the available 1/0 bandwidth of a processor is used less than 1% of the time.

We analyze the information content of several address reference streams.Our results indicate that a new scheme, based on Dynamic Huffman Coding [Vitt87], can encode a typical 32 bit address in four to seven bits.Unlike previous schemes used to estimate the information content of address words [HaDa771 ~arnm77], our scheme is completely on-line and does not rely on preeomputation of address transition probabilities.Our results imply that at least 83% of address bits in the traces we studied contain redundant information.Although our coding scheme is too complex and computationally expensive to implement in practice, it provides a lower bound on the bandwidth that can be achieved by practical compression schemes.Through use of these address compression techniques, the number of bus lines and 1/0 pins required to transmit address information between processor and memory can be ptly reduced.

Dynamic Base Register Caching (DBRC) FaFa90] lJhPa91] has been shown to be a useful technique for significantly reducing processor to memory address bandwidth.By caching the higher order portions of memory addresses in a set of dynamically allocated base registers, only small register indices need to be transmitted between the processor and memory instead of the high order address bits themselves.In this paper we present the results of trace driven simulations which indicate that DR13C can facilitate the provision of separate paths for instructions

This paper analyzes measurements of paging activity from several different versions of UNIX. We set out to characterize paging activity by first taking measurements of it, and then writing programs to analyze it. In doing so, we were interested in answering several questions:1. What is the magnitude of paging traffic and how much of I/O system activity is paging related?2. What are the characteristics of paging activity, and how can paging system implementations be tuned to match them?3. How does paging activity vary across different machines, operating systems, and job mixes?4. How well does paging activity correlate with system load average and number of users?

A PRAM (parallel random-access-machine) model that allows processors to have arbitrary asynchronous behavior is introduced. The main result shows that any n-processor CRCW (concurrent-read, concurrent-write) PRAM program can be simulated on an asynchronous CRCW PRAM using O(n) expected work per parallel step and up to n/log n log*n asynchronous processors. It is shown that a synchronization primitive for n parallel instructions can be computed using O(n) expected work by a system of asynchronous processors. Since a special case of asynchronous behavior is a fail-stop error, the simulation technique described above can convert any PRAM program into a PRAM program that is resistant to all fail-stop errors and has the same expected work as the original program.>

Paging performance can be a dominant factor in a program's running time. Many seemingly efficient data structures and algorithms lose orders of magnitude in performance because they generate an excessive number of page faults. This study shows that tradeoffs exist between average row access speed S/sub r/ (which is defined as the number of row elements retrieved divided by the number of blocks accessed) and average column access speed S/sub c/ (defined similarly). The authors prove that the S/sub r/S/sub c/ product is optimally bounded by the block size N and generalize to other access patterns. Practical array access strategies are developed, and extensions to these results are discussed.>

Two of the most important parameters of a computer are its processor speed and physical memory size. We study the relationship between these two parameters by experimentally evaluating the intrinsic memory and processor requirements of various applications. We also explore how hardware prices are changing the cost effectiveness of these two resources. Our results indicate that several important applications are “memory-bound,” i.e., can benefit more from increased memory than from a faster processor.