A well established analysis technique of low-pass Sigma-Delta modulators is based on the white noise model, where quantization noise is assumed a uniformly distributed random signal. However, Sigma-Delta modulators exhibit numerous nonlinear effects that the white noise model fails to explain. Recently, a different way of describing low-pass Sigma-Delta modulators has been developed, establishing its similarities with VCO-based ADCs. A key idea in this new representation is the concept of the Pulse Frequency Modulation equivalent of a low-pass Sigma-Delta modulator. This paper reviews this new description with a simplified and intuitive approach and proposes new applications of the PFM analysis to other Sigma-Delta modulator architectures such as Band-Pass and Multistage modulators.

Voltage controlled oscillators (VCOs) were demonstrated to be an efficient hardware alternative to analog integrators in supply constrained nanometer CMOS technologies. Notably, various filter designs have found applications in voice feature extraction and communication systems. However, a deep understanding of the trade-offs in their design and their system-level limitations has not yet been described. This paper proposes an analysis of linear filters approximated using VCO-based integrators and provides insights in the design aspects of these systems.

In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop configuration. A key enabler of the high-bandwidth MASH VCO ADC is the use of a multi-bit estimated error signal. With an OSR of 16, an SNDR of 67 dB and DR of 68 dB are achieved in 109.375 MHz bandwidth. The full-custom pseudo-analog circuits consume 9 mW, while the automatically generated digital circuits consume another 24 mW. A$\mathbf {FoM_{DR} = 163}$dB and core area of$\mathbf {0.017\,\mathbf {mm}^{2}}$are obtained.

Recently VCO-based filters have been used to implement feature extraction in voice recognition systems. Typically implemented filter structures embed the VCOs in a feedback loop. In these implementations, harmonic distortion has been observed in the output signal. This harmonic distortion has been attributed to ring oscillator nonlinearity but its origin stems from a system level problem. In this manuscript we will analyze this problem by looking at the cross modulation of Pulse Frequency Modulation (PFM) side-bands and we will explain how this creates the previously misunderstood harmonic distortion. Moreover, we will propose efficient techniques to mitigate these harmonic components and show that they can easily be implemented in hardware.

In this work, we focus on the Power Supply Rejection and Common Mode Rejection performance of inverter based ring oscillators intended for use in VCO ADCs. We show that they are closely related to the circuit’s mismatch behavior of which we perform a systematic analysis. To this end, we construct a theoretical mismatch model for these ring oscillators, based on Pelgrom’s mismatch model. In addition, we generalize this model to include the mismatch in a generic tuning circuit. In this broad analysis, we show that, next to the obvious transistor size dependence, the mismatch is inversely proportional to the number of stages and hence, in theory, can always be suppressed up to the desired level in a VCO ADC, provided that the tune circuit is sized adequately. Furthermore, we demonstrate that the mismatch is dependent on the biasing of the ring, which becomes even more apparent when taking into account the influence of a tuning circuit. More specifically, strong inversion is almost always better than weak inversion, and current control is preferred over voltage control. Finally, we perform extensive Monte Carlo simulations, with a commercially available 65nm CMOS process, which match our analytical predictions nearly perfectly.

Recently a study of the analog behavior of ring oscillators was presented from the perspective of VCO ADC design [1]. In this study it was shown that the electrical behavior between the two tuning terminals of such a ring oscillator can be modeled by a diode element. The VCO (phase-)noise can be modeled as an equivalent input-referred noise voltage source in series with this diode. Unfortunately, it was found that this input-referred noise was dependent on the driving impedance. In the prior study only ideal voltage and ideal current control were elaborated. In this work, we generalize the VCO noise model for an arbitrary driving impedance. This enables the noise optimization of a VCO with an arbitrary driving circuit which was not possible with the prior theory. In this work we present such a noise optimization for the linearizing resistive VCO drive circuit of [2], [3]. We show that for this circuit the biasing of the ring is rather uncritical, which is in strong contrast with the result for a pure voltage mode drive circuit, where the biasing of the ring has a major impact on the noise performance.

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1st-order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account.

In this work, we focus on the three most relevant pseudo-digital ring oscillator circuits for VCO A/D conversion. First, we show that they can be accurately modeled by an equivalent 2-terminal diode-like element. Next, we study the main analog performance figures: the effective oscillation frequency (which affects the quantization noise of a VCO ADC), the input referred noise and the power efficiency both for voltage and current control. We do this both through theoretical modeling as well as through simulations, which are in good agreement with each other. Our study highlights several important independencies: e.g. most performance metrics are independent on the number of VCO stages and the external load capacitance on the VCO nodes. In contrast to these independencies, we identify several important dependencies. In particular, we show that the biasing of the ring has an enormous impact on power efficiency of the ring. This dependency is different for the case of a voltage- or current mode configuration of the ring.

Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in such a CDR is the phase detector which should detect whether the recovered clock leads or lags the incoming data edges. In typical implementations an incoming data edge is detected by sensing whether the incoming waveform crosses a data threshold level. However, there is some ambiguity in detecting the incoming data edge because PAM-4 modulation has 3 thresholds. If the waveform crosses multiple threshold levels, the level crossings will occur at different time instants due to the finite rise/fall time of the incoming waveform. In this work, we first analyze qualitatively and quantitatively CDR systems that use one threshold for phase adjustment. Here, eliminating the 2-level transitions decreases the amount of jitter injected by the phase detector. However, the available transitions for phase adjustment are also reduced, which lowers the CDR's robustness. Secondly, for CDR systems using three thresholds, a combination of two techniques: majority voting and elimination of 2-level transitions is investigated. We prove that in this case, the elimination of 2-level transitions is not needed and even gives a worse performance when implemented.

This work describes a systematic way to implement a band-pass noise-transfer-function (NTF) in an analog-to-digital converter implemented with a voltage-controlled-oscillator (VCO-ADC). The approach is based on the pulse frequency modulation (PFM) interpretation of a VCO-ADC, where the NTF is defined by a suitable pulse shaping filter inserted after the VCO. In this work, we explain how this pulse shaping filter can be defined to implement a quadrature band-pass NTF. In addition to describing the best theoretical way to achieve this, we also propose a hardware implementation using a digital delay line whose outputs are decoded with two lookup tables (LUTs). This enables tuning the NTF in software. Transient simulations were made to validate the implementation and robustness of the proposed approach and a case study of the power consumption was made for the case of a 65-nm CMOS process. Due to the mostly digital circuit implementation, the proposed structure is suitable for even newer ultra deep submicron CMOS processes.

We present a closed loop architecture for readout of Wheatstone bridge sensors. A key enabler of the proposed architecture is the floating bridge biasing technique. Thanks to this, the bridge's sense nodes can easily be read out in current mode. This current mode read-out in turn makes it very easy to convert the read-out front end amplifier of the bridge into an integrator. This integrator can then conveniently be used as the first integrator in a ΣΔ modulation feedback loop that can be set up around the sensor. This way we end up with a closed loop feedback system which has inherent A/D-conversion. We studied several design concerns in this system and explained how they could be overcome. Transistor level simulations confirm that the system can achieve adequate performance.

Recently an architecture for a nearly digital VCO ADC with high order quantization noise shaping was presented. Unfortunately, the structure is affected by the non-linearity of the first VCO. In this manuscript, we report experimental results of a potential solution for this problem: placing a pulse width modulator (PWM) in front of this first VCO. The work is based on a prototype VCO-ADC with 3rd order noise shaping and 10 MHz bandwidth, implemented in a 65 nm CMOS technology. For small input signals the circuit behaves as expected. Unfortunately for larger input signal levels the noise of the prototype is significantly higher than was expected from the a priori simulations. Upon investigation, this is attributed to subtle (mismatch induced) intermodulation effects. Overall the prototype's measured performance leads to a DR/SNR/SNDR of 67.4/59/55.4 dB at a 10MHz bandwidth while consuming 2.3mW from a 1.0V analog and 2mW from a 1.2V digital supply.

Recently nearly exact expressions for the distortion in a commonly used family of Pulse Width Modulators (PWMs) known as Asynchronous Sigma Delta Modulators (ASDMs) were presented. Such an ASDM consists of a feedback loop with a schmitt-trigger (or a comparator), and a continuous time loop filter. However these previous results are not yet practically applicable because the effect of unavoidable loop delay (e.g. in the schmitt trigger) was not taken into account. Therefore we now present a more general theory that is also valid when there is a nonzero loop delay. A comparison of the resulting equations with computer simulations demonstrated a very good matching, confirming the validness of the theory. This way, a designer can now easily understand the relationship between the loop filter dynamics and the linearity of an ASDM.

We present an offline calibration method to correct the non-linearity due to DAC element mismatch in distributed feedback SigmaDelta-modulation A/D-converters. The improvement over previous methods is that not only the first feedback DAC is calibrated, but also the DACs that are coupled to later stages can be calibrated as well. This is needed in the case of Sigma Delta modulators with a low OSR, where the contribution of the second feedback DAC should not be neglected. The technique is based on a calibration measurement with a two-tone input signal.

It is well known that the performance of current-steering D/A converters (DACs) is affected by parasitic effects such as static device mismatch and dynamic timing mismatch. Typically, this results into about 10-bit peak performance. To increase this number, the designer has two options: either use a very large silicon area to obtain better matching, or alternatively use a (sophisticated) calibration technique. In this paper we present a D/A converter circuit with a “Redundant Signed Digit” (RSD) coding scheme for binary weighted D/A conversion. This scheme does not really improve the peak performance for full-scale input signals. E.g with a full-scale 3.2 MHz 14-bit input sinusoidal signal, the SFDR equals 60 dB for our circuit. But the performance is only gradually reduced for small input signals: for a -43 dB 14-bit input signal the SFDR is still 44 dB, which is close to the performance of an ideal 14-bit D/A converter. The analog section of this circuit was implemented in a standard 0.18 m (1P6M) CMOS process and requires only 0.1 mm2of silicon area.

The accuracy of high-speed DAC's is limited by dynamic effects such as glitches. Here, a digital calibration technique to compensate this effect is presented. Because of the digital approach, this solution can not be an exact correction of the phenomenon, but band limited attenuation. The approach consists of adding a (digital) compensation signal to correct the glitch. Both a 2-tap and a 4-tap correction are investigated and it is shown that they can greatly reduce spurs over a bandwidth of 30% and 60% of the Nyquist band respectively, provided the glitch energy is known. Next, it is shown how an adaptive calibration with an additional low-speed calibration ADC can be used to estimate the glitch energy. Simulations confirm that the spectral performance can be greatly improved this way.

ΣΔ force-feedback loops have to deal with a stability problem due to phase-lag occurring in the sensor. To tackle this problem traditionally a compensator is introduced in the loop. We show that this traditional approach imposes a constraint on the realizable NTF such that the NTF cannot be optimized. Next we propose a novel unconstrained architecture that allows to implement any NTF. This way greatly improved quantisation noise shaping can be obtained. In a typical design example the improvement was 12 dB.

QuadratureΣΔADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with near-perfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that should be shaped out of the signal band with dynamic element-matching (DEM) techniques. In literature, only quadrature DEM techniques for 3-state (I, Q, 0) unit elements are considered. However, in fully differential circuit, also 5-state unit elements are available. In this case, each unit element can be selected ±1, ±Q or 0. When using these 5-state unit elements, the amount of hardware and power consumption can be reduced significantly. In this paper it is shown how the tree structure, the data directed swapper and the vector quantizer structure can be adapted for the use in fully differential circuits with such 5-state unit elements.

This work presents experimental results of a 6th order band-pass continuous-time sigma-delta modulator that uses transmission lines as resonators. It has been implemented in 0.35mum SiGe BiCMOS technology. The modulator tolerates two clock cycles of excess loop delay and has similar clock jitter sensitivity to that of an equivalent switched capacitor solution. The ADC operates at a sampling rate of fs=184 MHz, consumes 62mW and, assuming an OSR=256, is able to convert with a maximum SNR=55dB signals centered both at 46 MHz and 138 MHz, due to its subsampling capabilities

In this paper we propose a way to design continuous time SigmaDelta modulators. The method is based on the Nyquist stability criterion. Based on this criterion we propose to use the vector gain margin as a robust stability margin. Using this margin as a design criterion we design a robustly stable modulator. Finally, we also show how this margin can be used to evaluate the relative stability of a designed modulator

Quadrature SigmaDelta ADCs require a feedback path for both the I and the Q part of the complex feedback signal. If two separated multibit feedback DACs are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an unbalance between the I and Q DAC. This paper proposes a new quadrature bandpass mismatch shaping technique. In our approach the I and Q DACs are merged into one complex DAC, which leads to near-perfect I/Q balance. To select the unit DAC elements of the complex, multibit DAC, the well-known tree structured element selection logic is generalized toward a complex structure and necessary conditions for its correct operation are derived. Finally, a very efficient first-order quadrature shaper implementation is proposed and simulations show the effectiveness of the quadrature bandpass mismatch shaping technique