Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas H. Bredt
dblp:59/7037
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 1976
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 3Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Embedded and real-time systems · 35% Distributed systems · 24% Electronic design automation · 17% | |
| Software engineering, system software, and programming languages
2 papers |
Program verification · 46% Operating systems · 40% Program analysis · 14% |
Topics — the 10 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems
real-time system design |
0.0 | 1 | 1976 | Design and Verification of Real-Time Systems · ICSE 1976 |
Embedded and real-time systems
real-time system verification |
0.0 | 1 | 1976 | Design and Verification of Real-Time Systems · ICSE 1976 |
Operating systems
interprocess communication |
0.0 | 1 | 1975 | Error Resynchronization in Producer-Consumer Systems · SOSP 1975 |
Hardware reliability and fault tolerance
error recovery |
0.0 | 1 | 1975 | Error Resynchronization in Producer-Consumer Systems · SOSP 1975 |
Distributed systems
fault tolerance |
0.0 | 1 | 1975 | Error Resynchronization in Producer-Consumer Systems · SOSP 1975 |
Parallel and multicore computing
concurrent system |
0.0 | 1 | 1971 | Analysis of Parallel Systems · IEEE Trans. Computers 1971 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1971 | Analysis of Parallel Systems · IEEE Trans. Computers 1971 |
Electronic design automation › hardware verification and test
hazard analysis |
0.0 | 1 | 1971 | Analysis of Parallel Systems · IEEE Trans. Computers 1971 |
Distributed systems
mutual exclusion |
0.0 | 1 | 1971 | Analysis of Parallel Systems · IEEE Trans. Computers 1971 |
Program analysis › dynamic analysis
runtime monitoring |
0.0 | 1 | 1976 | Verification of a Monitor Specification · ICSE 1976 |
Methods — techniques the papers use, named apart from their topics
error processing · 0.0state graph analysis · 0.0flow table model · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1976 | Design and Verification of Real-Time Systems
J. V. Phillips, Thomas H. Bredt |
ICSE | 2 |
| 1976 | Verification of a Monitor Specification
Ashok R. Saxena, Thomas H. Bredt |
ICSE | 2 |
| 1975 | Error Resynchronization in Producer-Consumer SystemsabstractThis paper is concerned with error processing for parallel producer-consumer interactions such as encountered in the desing of multi-process operating systems. Solutions to resynchronization problems that occur when a consumer process detects errors in information received from a producer process are presented. Fundamental properties of this error processing are discussed. It is shown that explicit error processing results in an increase in program complexity and a decrease in the ease of understanding a program. David L. Russell, Thomas H. Bredt |
SOSP | 2 |
| 1971 | Analysis of Parallel SystemsabstractA formal analysis procedure for hardware and software computer systems is described. A system is described by a flow table model. The concept of an output hazard is introduced to account for effects of unbounded line delays. Necessary and sufficient conditions for the absence of output hazards are given. A system that contains no output hazards is said to operate correctly if the system state graph that describes all system states and state transitions is free from forbidden states and forbidden state sequences. A flow table solution for the two-component mutual exclusion problem is analyzed and shown to be correct. Thomas H. Bredt |
IEEE Trans. Computers | 1 |