Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power performance (up to -24%).

Multiplicative Newton–Raphson and Goldschmidt algorithms are widely used in current processors to implement division, reciprocal, square root and square root reciprocal operations. Based on an initial approximation of a given accuracy, several iterations are performed until the required result accuracy is achieved. The number of iterations depends on the initial approximation and on the required accuracy. Each iteration consists of several multiplications. In this paper, we present an accurate error analysis that takes into account all the contributions to the final error and allows us to obtain error bounds for each iteration. These error bounds can be used to obtain optimal unit designs by reducing the size of the multiplier and, therefore, to reduce the area requirements. To show the usefulness of the error analysis, we compare the optimal multiplier size obtained from our error analysis with the multipliers in the floating-point division and square root units of some popular processors and we conclude that the multiplier size and its area can be reduced by, roughly, 10%.

A new variable latency Goldschmidt algorithm is presented. The algorithm is based on a new rounding method for division, square root, and their reciprocals that avoids the conventional remainder calculation in most of cases and improves previous proposals. The rounding decision is taken by checking the least significant bits of the output of the last Goldschmidt iteration without any other transformation. This helps to reduce the number of cases which need the calculation of the remainder. Additionally, we avoid the calculation of the remainder for most of those cases by using a remainder estimate that can be easily obtained from the Goldschmidt iteration. The calculation of the estimate is much simpler and less time consuming than the calculation of the remainder and this contributes to reducing the number of cases which need a large latency. The combination of both techniques allows us to define a variable latency algorithm which needs to compute the remainder in just nine percent of the total number of cases for reciprocal and division and in 12 percent for square root and square root reciprocal.

This paper presents a rounding method for functional iteration algorithms. The new method is made up of a new rounding algorithm and the calculation of a remainder estimation. The rounding method uses the result directly obtained from the algorithm without any transformation. The remainder estimation is calculated in parallel with the algorithm execution. This allow us to avoid the conventional remainder calculation after obtaining result, most of the times. In this way, the final implementation has a variable latency. By using adequate configurations the remainder calculation is only necessary in 9% of the total cases.

The aim of this work is to present a method for rounding quadratically converging algorithms that improves their performance. This method is able to reduce significantly the number of cases where the remainder calculation is necessary. It is based on previous methods and incorporates additional bits of the result approximation to be checked. This work includes the result of exhaustive simulations that permit us to measure exactly how many calculations are avoided. Using these simulations, it is concluded that the presented method is able to reduce by half the number of remainder calculations. Using adequate result approximations the remainder calculation is necessary in only 5% of the total cases.

An analysis of the impact of different methods for the double-precision computation of division and square root in the performance of a superscalar processor is presented in this paper. This analysis is carried out combining the SimpleScalar toolset, estimates of the latency and throughput of the compared methods and a set of benchmarks with typical features of intensive computing applications. Simulation results show the importance of having an efficient unit for the computation of these operations, since changes in the density of division and square root below 1% lead to changes in the performance around a 20%.