As smart environments become laden with more and more sensors, there has been a need to develop systems that could derive useful information from these sensors and make the smart environments smarter. Complex Event Processing (CEP) has emerged as a popular strategy to identify crucial events from sensor data. However, the existing CEP strategies overlook the relationship with other sensors in the spatial vicinity and understate the temporal variation of sensor data. In this paper, we develop RACER, which is an end-to-end complex event processing system that takes into consideration both the spatial location of the sensor in observation and the varying impact of temporal changes in the sensor data. Experiments performed for a duration of five months over both collected and live streaming data shows that RACER fares well compared to the other state-of-the-art approaches.

IoT is developing rapidly with frequently appearing new wireless standards and applications. However, besides a large number of IoT benefits, its further development is now being slowed down due to the repetition of old Internet development flaws while dealing with IoT heterogeneity. The current misleading trend aims to solve all IoT interoperation problems by inserting IP Addresses into those wireless protocols where the IP stack clearly slows down application performance and drains the battery, e.g. LPWANs such as LoRaWAN and SigFox. This paper tackles IoT heterogeneity from a different perspective: it is the application interoperation which matters the most. The protocols beneath the application layer shall work for smooth upper-layer service provisioning where the IP shall be just one of the many underlying integration options instead of being the essential one. Inspired by previous proposals for a more flexible internetworking architecture, this paper applies those theoretical concepts in practice by proposing a protocol-independent distributed interoperation model for smooth service provisioning over heterogeneous IoT wireless contexts. The arguments pro the IP-agnostic IoT application interoperation are supported by the model's prototype which showed 1.6-2 times faster MQTT application operation over LoRa and WiFi compared to the legacy IP-based MQTT provisioning over that protocols.

Arrays computations are at the core of numerical modelling and computational science applications. However, low-level manipulation of array indices is a source of program error. Many practitioners are aware of the need to ensure program correctness, yet very few of the techniques from the programming research community are applied by scientists. We aim to change that by providing targetted lightweight verification techniques for scientific code. We focus on the all too common mistake of array offset errors as a generalisation of off-by-one errors. Firstly, we report on a code analysis study on eleven real-world computational science code base, identifying common idioms of array usage and their spatial properties. This provides much needed data on array programming idioms common in scientific code. From this data, we designed a lightweight declarative specification language capturing the majority of array access patterns via a small set of combinators. We detail a semantic model, and the design and implementation of a verification tool for our specification language, which both checks and infers specifications. We evaluate our tool on our corpus of scientific code. Using the inference mode, we found roughly 87,000 targets for specification across roughly 1.1 million lines of code, showing that the vast majority of array computations read from arrays in a pattern with a simple, regular, static shape. We also studied the commit logs of one of our corpus packages, finding past bug fixes for which our specification system distinguishes the change and thus could have been applied to detect such bugs.

Multi- and many-core processors are becoming increasingly popular in embedded systems. Many of these processors now feature hardware virtualization capabilities, as found on the ARM Cortex A15 and x86 architectures with Intel VT-x or AMD-V support. Hardware virtualization provides a way to partition physical resources, including processor cores, memory, and I/O devices, among guest virtual machines (VMs). Each VM is then able to host tasks of a specific criticality level, as part of a mixed-criticality system with different timing and safety requirements. However, traditional virtual machine systems are inappropriate for mixed-criticality computing. They use hypervisors to schedule separate VMs on physical processor cores. The costs of trapping into hypervisors to multiplex and manage machine physical resources on behalf of separate guests are too expensive for many time-critical tasks. Additionally, traditional hypervisors have memory footprints that are often too large for many embedded computing systems. In this article, we discuss the design of the Quest-V separation kernel, which partitions services of different criticality levels across separate VMs, or sandboxes . Each sandbox encapsulates a subset of machine physical resources that it manages without requiring intervention from a hypervisor. In Quest-V, a hypervisor is only needed to bootstrap the system, recover from certain faults, and establish communication channels between sandboxes. This not only reduces the memory footprint of the most privileged protection domain but also removes it from the control path during normal system operation, thereby heightening security.

This paper describes the scheduling framework for a new operating system called "Quest". The three main goals of Quest are to ensure safety, predictability and efficiency of software execution. For this paper, we focus on one aspect of predictability, involving the integrated management of tasks and I/O events such as interrupts. Quest's scheduling infrastructure is based around the concept of a virtual CPU (VCPU). Using both Main and I/O VCPUs, we are able to separate the CPU bandwidth consumed by tasks from that used to complete I/O processing. We introduce a priority-inheritance bandwidth-preserving server policy for I/O management, called PIBS. We show how PIBS operates with lower cost and higher throughput than a comparable Sporadic Server for managing I/O transfers that require small bursts of CPU time. Using a hybrid system of Sporadic Servers for Main VCPUs, and PIBS for I/O VCPUs, we show how to maintain temporal isolation between multiple tasks and I/O transfers from different devices. We believe Quest's VCPU scheduling infrastructure is scalable enough to operate on systems supporting large numbers of threads. For a system of 24 Main VCPUs, we observe a CPU scheduling overhead of approximately 0.3% when VCPU budget is managed in 1ms units.