Yicheng Li 0002

dblp:59/8179-2 · DBLP profile ↗
← Back
4ranked-venue papers
0as first author
4since 2021 · last 2025
0000-0003-4447-7452ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
YearPublicationVenuePosition
2025 Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTM
abstract
For the first time, this paper presents an unsupervised learning residual long short-term memory (ULR_LSTM) neural network to develop a digital predistortion (DPD) method for the linearization of digital power amplifiers (DPAs). Our method eliminates the need for iterative learning control (ILC) to obtain the ideal input of the DPA required by state-of-the-arts (SOTAs), which leads to high computational complexity and extensive training time. We perform behavioral modeling of the DPA using the R_LSTM network. After determining the optimal behavioral model architecture, the corresponding DPD model is obtained through an inverse training process. A 15-bit transformer-based quadrature DPA chip incorporating Class-G and IQ-cell-sharing techniques was implemented in a 28nm CMOS process to validate our proposed method. Experimental results demonstrate outstanding linearization performance comparing to prior arts, achieving an error vector magnitude (EVM) of -40.4dB for the 802.11ax 40MHz 64QAM signal.
Luyi Guo, Yicheng Li 0002, Wang Wang, Manni Li, Zijian Huang 0017, Yinyin Lin, Yun Yin, Hongtao Xu
DATE3
2025 Digital Predistortion for Quadrature Digital Power Amplifiers Using Deep Neural Network of AT_LSTM: Attention LSTM
Wending Zhao, Yicheng Li 0002, Wang Wang, Manni Li, Zijian Huang 0017, Yinyin Lin, Yun Yin, Hongtao Xu
ACM Great Lakes Symposium on VLSI3
2025 Digital Predistortion for Wide Dynamic Power Range Quadrature Switched-Capacitor Power Amplifiers Using Self-Adaptive Residual LSTM Neural Network
Luyi Guo, Yicheng Li 0002, Yinyin Lin, Yun Yin, Hongtao Xu
IEEE Trans. Very Large Scale Integr. Syst.3
2024 Nonlinear Analysis of Quadrature Switched-Capacitor Power Amplifier and Digital Predistortion
abstract
This paper presents a modified vector combination (MVC) model to analyze the nonlinearity behavior in the quadrature switched-capacitor power amplifier (SCPA), which improves model accuracy while reducing the number of recorded points and iterations compared to the two-dimensional (2-D) LUT-based model. To analyze the nonlinearity caused by efficiency enhancement techniques, high-order Taylor series are applied to meet the model accuracy requirement. Moreover, a two-stage process with MVC and general memory polynomial (GMP) digital predistortion (DPD) is introduced to calibrate the static nonlinearity and memory effect, respectively. In the measurement, a 15-bit transformer-based quadrature SCPA chip with Class-G and IQ-cell-sharing techniques is implemented in 28nm CMOS and employed to verify the effectiveness of the MVC and two-stage DPD methods. For the 802.11ax 40MHz 64QAM signal at 2.4GHz, this chip achieves up to −40.9dB error vector magnitude (EVM) floor and significant EVM improvement even at deep power back-offs after the DPD.
Fu Gao, Luyi Guo, Yicheng Li 0002, Yun Yin, Hongtao Xu
IEEE Trans. Circuits Syst. I Regul. Pap.3