The advancement of quantum computing into the utility scale requires compilation frameworks that can effectively manage the discrepancy between high-level algorithmic intent and the low-level physical constraints of contemporary hardware. Quantum circuit partitioning is a pivotal stage in this compilation pipeline, particularly when leveraging high-performance synthesis tools that are computationally bounded by the number of qubits. Existing partitioning approaches, such as ScanPartitioner [19] and QuickPartitioner [21], while effective, do not leverage structural patterns in circuits, limiting their ability to make globally informed local partitioning decisions. To address this gap, we propose a novel structural-aware quantum circuit partitioning method using a reinforcement learning (RL) framework that harnesses global circuit knowledge to guide local partitioning decisions, enabling more optimization opportunities at the sub-circuit level. Experimental results on benchmark circuits transpiled to satisfy IBM quantum hardware constraints show that our approach reduces the native two-qubit gate count compared to existing quantum circuit partitioners (ScanPartitioner and QuickPartitioner) with an average two-qubit gate reduction of 18.55% over baselines. This research establishes a scalable and robust methodology for partitioning quantum circuits, bridging the gap between exact and approximate synthesis in the Noisy Intermediate-Scale Quantum (NISQ) era and beyond.

To generate physical quantum circuits, quantum gates are often added to the quantum circuit to satisfy the hardware constraints. This process is called quantum circuit mapping. Noise-aware mapping techniques generate physical quantum circuits for noisy intermediate-scale quantum (NISQ) computers. However, the absence of an accurate noise model of the quantum hardware limits its performance. In this article, we propose a noise adaptive quantum circuit mapping approach using reinforcement learning (RL) and graph neural network (GNN)-based reliability predictor. Our RL agent learns a quantum circuit mapping policy that significantly improves the quantum circuit output fidelity by interacting with the environment, which adopts a GNN reliability model that acts as quantum hardware and estimates the physical quantum circuit fidelity. Furthermore, we propose a multi-GNN reliability model to speed up the inference while maintaining high accuracy. Our proposed RL framework fills the gap between the simplified reliability models of the quantum hardware and the realistic noise impact of the quantum hardware on the quantum circuits. We demonstrate the improvement in the output fidelity of quantum circuits generated using our approach compared to other quantum circuit mapping techniques across different real-world quantum hardware using multiple-seed experiments.

The current advancement in quantum computers has been focusing on increasing the number of qubits and enhancing their fidelity. However, the available quantum devices, known as intermediate scale quantum (NISQ) computers, still suffer from different sources of noise that impact their reliability. Thus, practical noise modeling is of great importance in the development of quantum error mitigation approaches. In this article, we propose a machine learning (ML)-based scheme to predict the output fidelity of the quantum circuit executed on NISQ devices. We show the benefit of using graph neural network (GNN)-based models compared to traditional ML-based models in capturing the quantum circuit structure in addition to its gates’ features, which enable characterizing unpredicted quantum circuit errors. We use different metrics to measure the fidelity of the quantum circuit output. Our experimental results using different quantum algorithms executed on IBM Q Guadalupe quantum computer show the high prediction accuracy of our ML reliability models. Our results also show that our models can guide the single-qubit gate rescheduling to improve the output fidelity of the quantum circuit without the need for prior execution of dedicated calibration circuits.

Dynamical Decoupling (DD)-based protocols have been shown to reduce the idling errors encountered in quantum circuits. However, the current research in suppressing idling qubit errors suffers from scalability issues due to the large number of tuning quantum circuits that should be executed first to find the locations of the DD sequences in the target quantum circuit, which boost the output state fidelity. This process becomes tedious as the size of the quantum circuit increases. To address this challenge, we propose a Graph Neural Network (GNN) framework, which mitigates idling errors through an efficient insertion of DD sequences into quantum circuits by modeling their impact at different idle qubit windows. Our paper targets maximizing the benefit of DD sequences using a limited number of tuning circuits. We propose to classify the idle qubit windows into critical and non-critical (benign) windows using a data-driven reliability model. Our results obtained from IBM Lagos quantum computer show that our proposed GNN models, which determine the locations of DD sequences in the quantum circuits, significantly improve the output state fidelity by a factor of 1.4x on average and up to 2.6x compared to the adaptive DD approach, which searches for the best locations of DD sequences at run-time.

The development of near-term quantum computers, referred to as Noisy Intermediate-Scale Quantum (NISQ) computers, has progressed rapidly in the past few years resulting in several quantum computers which vary in their underlying technology and physical constraints. The performance of these computers also varies from one quantum algorithm to another. To enable efficient selection of the quantum computer that provides the highest output fidelity for a given application, an accurate noise modeling of each quantum hardware is required. However, noise modeling for a given application is a complex problem because of the unknown interaction between the quantum circuit parameters and the noise parameters of NISQ devices. We propose the use of Machine Learning (ML) to model the performance of different quantum computers at the application level. The ML models predict the output fidelity of the quantum application executed on different quantum computers given their publicly available physical constraints. We use a diverse training dataset to cover the key features for application-level benchmarking of the quantum hardware. Our results obtained from different superconducting quantum devices show that our proposed ML models enable cost-effective quantum computer selection for different quantum applications with different fidelity metrics.

Noisy Intermediate-Scale Quantum (NISQ) computers consisting of tens of inherently noisy quantum bits (qubits) suffer from reliability problems. Qubits and their gates are susceptible to various types of errors. Due to limited numbers of qubits and high error rates, quantum error correction cannot be applied. Physical constraints of quantum hardware including the error rates are used to guide the design and the layout of quantum circuits. The error rates determine the selection of qubits and their operations. The resulting circuit is executed on the quantum computer. This study explores the risk of unexpected changes in the error rates of NISQ computers post-calibration. We show that unexpected changes in error rates can alter the output state of a quantum circuit. To detect these changes, we propose the insertion of test points into the quantum circuit to enable online monitoring of the physical qubit behavior. We utilize classical, superposition, and uncompute test points. Furthermore, we use a gate error coverage metric to assess the quality of the tests. We verify the effectiveness of the proposed scheme on different IBM quantum computers (IBM Q), in addition to a noisy simulation that shows the scalability of the proposed approach.

While current quantum computers, referred to as Noisy Intermediate-Scale Quantum (NISQ) computers, are expected to be beneficial for different applications, they are prone to different types of errors. In order to enhance the reliability of quantum systems, noise-aware quantum compilers are used to generate physical quantum circuits to be executed on NISQ computers. The quantum hardware is calibrated very frequently and its error rates are computed accordingly. Based on the hardware error rates, a quantum compiler allocates physical qubits and schedules quantum operations. However, error rates may change post-calibration. To incorporate dynamic error rates into quantum circuit compilation with minimum cost, we propose a Machine Learning (ML)-based scheme to detect the incorrect output of the quantum circuit and predict the Probability of Successful Trials (PST) with high accuracy. Our approach can verify the error rates of the quantum hardware and validate the correctness of the extracted quantum circuit output. We provide a case study of our ML-based reliability models using IBM Q16 Melbourne quantum computer. Our results show that the proposed scheme achieves a very high prediction accuracy.

Despite the current progress in quantum computing, the reliability of quantum computers is very challenging. Near-term quantum computers referred to as Noisy Intermediate-Scale Quantum (NISQ) computers are expected to operate in the presence of errors. To run a quantum circuit on a NISQ computer, the circuit should be mapped to satisfy the physical constraints of the quantum architecture. The mapping process takes into account the error rates of the quantum hardware. It selects physical qubits and their movements, which minimize the circuit error rates. The output of the quantum circuit can be obtained through several runs on NISQ computers.

Reversible circuits employ a computational paradigm that is beneficial for several applications, including the design of encoding and decoding devices, low-power design, and emerging applications inquantum computation. However, similarly to conventional logic, reversible circuits are expected to be subject toIntellectual Property/Integrated Circuit piracy. To counteract such attacks, an understanding of how to identify the target function from a reversible circuit is a crucial first step. In contrast to conventional logic, the target function is (implicitly or explicitly) embedded into the reversible circuit. Numerous synthesis approaches have been proposed for this embedding task. To recover the target function embedded in a reversible circuit, one needs to know what synthesis approach has been used to embed the circuit. We propose a machine-learning-based scheme to determine the used reversible synthesis approach based on the telltale signs it leaves in the synthesized reversible circuit. We study the impact of optimizing the synthesis approaches on the telltale signs that they leave. Our analysis shows that the synthesis approaches can be determined in the vast majority of cases even if optimized versions of the synthesis approaches are used.

The research community expects that quantum computers will give economical results for particular problems on which the classical computers break down. Examples include factoring of large numbers, searching in a big database, or simulating chemical reactions to design new drugs. Attempts are ongoing to build up a practical quantum computer. Users (clients) can implement quantum circuits to run on these quantum computers. However, before running the quantum circuit on the quantum computer, the users (clients) should compile, optimize, decompose, and technology map the quantum circuit. In the current embodiment, the resulting quantum circuit runs on a remote and untrusted quantum computer server -- introducing security risks. This study explores the risk of outsourcing the quantum circuit to the quantum computer by focusing on quantum oracles. Quantum oracles are pivotal building blocks and require specialized expertise and means to design. Hence, the designer may protect this proprietary quantum oracle intellectual property (IP) and hide his/her private information. We investigate how to manage that on a quantum computer server using the IBM project QX quantum computer and Qiskit tools as an exemplar.

Fabless semiconductor companies design system-on-chips (SoC) by using third-party intellectual property (IP) cores and fabricate them in offshore, potentially untrustworthy foundries. Owing to the globally distributed electronics supply chain, security has emerged as a serious concern. In this article, we explore electronics computer-aided design (CAD) software as a threat vector that can be exploited to introduce vulnerabilities into the SoC. We show that all electronics CAD tools—high-level synthesis, logic synthesis, physical design, verification, test, and post-silicon validation—are potential threat vectors to different degrees. We have demonstrated CAD-based attacks on several benchmarks, including the commercial ARM Cortex M0 processor [1].

Reversible circuits employ a computing paradigm that is useful in a broad variety of applications. With increasing interest, security concerns for those circuits also will rise in the near future. At first glance, reversible circuits seem to be more secure to integrated circuit (IC)/intellectual property (IP) piracy than conventional circuits, since the target function is usually embedded in the reversible backbone circuit. This embedding adds ancillary inputs and garbage outputs that may appear to hide the target function. However, recent work showed that target function embedding and reversible synthesis methods leave telltale signs in the reversible circuits, which allow for an easy extraction of the synthesis approach and the embedded circuit. In this article, we perform an analysis of the IC/IP piracy attacks on reversible circuits. We focus on the reversible circuits generated by the quantum multivalued decision diagram (QMDD)- and binary decision diagram (BDD)-based synthesis approaches as case studies. We show that most of the target function can be identified using the telltale signs of the synthesis approach. We then propose a cost-effective input-output scrambling scheme that wipes out these telltale signs and, thus, thwarts the considered attacks by adding reversible gates. Those additional gates yield efficient yet secure reversible circuits.

Reversible logic is a building block for adiabatic and quantum computing in addition to other applications. Since common functions are non-reversible, one needs to embed them into proper-size reversible functions by adding ancillary inputs and garbage outputs. We explore the Intellectual Property (IP) piracy of reversible circuits. The number of embeddings of regular functions in a reversible function and the percent of leaked ancillary inputs measure the difficulty of recovering the embedded function. To illustrate the key concepts, we study reversible logic circuits designed using reversible logic synthesis tools based on Binary Decision Diagrams and Quantum Multi-valued Decision Diagrams.

Reversible circuits are vulnerable to intellectual property and integrated circuit piracy. To show these vulnerabilities, a detailed understanding on how to identify the function embedded in a reversible circuit is crucial. To obtain the embedded function, one needs to know the synthesis approach used to generate the reversible circuit in the first place. We present a machine learning based scheme to identify the synthesis approach using telltale signs in the design.

NEMS relay technology is a promising class of emerging devices that offer zero static leakage and hence overcomes the power dissipation issues of deep-submicron CMOS technology devices. As NEMS relay based digital circuits have potentially higher energy-efficiency than those based on CMOS transistors, circuits based on NEMS relay device are worth exploring. However, NEMS relay devices suffer from large delay compared to CMOS technology; Binary Decision Diagram (BDD) based implementation targets to minimize the total circuit delay, fixing this problem. However, such an implementation renders the timing delay of a NEMS based circuit input-dependent, which can be exploited to infer on-chip secret information from delay information. In this presentation, we illustrate these security vulnerabilities and present countermeasures for a recently proposed energy-efficient block cipher Midori128 that has an on-chip secret key that needs to be protected.

In deep submicron CMOS transistors, the static leakage current has become a significant contributor to power consumption with channel length and subthreshold voltage being continuously scaled down. Also, this increased leakage has recently led to the rise of side-channel attacks on CMOS based implementations. Nanoelectromechanical System (NEMS) relay technology is emerging as an alternative to CMOS with one of its most prominent advantages being the zero static leakage, providing an inherent defense against power side-channel attacks at the same time. On the other hand, this emerging technology introduces timing challenges in the design process; to minimize the timing delay of NEMS relays, binary decision diagram (BDD) based implementation is utilized to design combinational logic. What's important from a security perspective is that the timing delay of the BDD implementation of a NEMS relay based design is inherently input dependent. An adversary can therefore leverage the data dependency to identify secret information of the chip. We propose a timing delay based attack on NEMS relay based designs, use AES as a case study, and show that it can achieve a success rate of 1.0 for interconnect delay variations within a standard deviation of 0.0022. To the best of our knowledge, this paper is the first to expose an inherent security vulnerability of a NEMS relay based design.

Scan design is a de facto design-for-testability (DfT) technique that enhances access during manufacturing test process. However, it can also be used as a back door to leak secret information from a secure chip. In existing scan attacks, the secret key of a secure chip is retrieved by using both the functional mode and the test mode of the chip. These attacks can be thwarted by applying a reset operation when there is a switch of mode. However, the mode-reset countermeasure can be thwarted by using only the test mode of a secure chip. In this paper, we perform a detailed analysis on the test-mode-only scan attack. We propose attacks on an advanced encryption standard (AES) design with a basic scan architecture as well as on an AES design with an advanced DfT infrastructure that comprises decompressors and compactors. The attack results show that indeed the secure chips are vulnerable to test-mode-only attacks. The secret key can be recovered within 1 s even in the presence of decompressors and compactors. We then propose new countermeasures to thwart these attacks. The proposed countermeasures incur minimal cost while providing high success rate.

While manufacturing test necessitates deep access into the Integrated Circuit (IC) to enhance its testability, this can inadvertently threaten the security of the IC in security-critical applications. Although black-box testing ensures security, it fails to deliver high-quality test. Therefore, our goal is to come up with DFT techniques that deliver testability without compromising the security of the IC. We propose various DFT techniques that tackle the testing challenges, such as test time, test data volume, and test power. Furthermore, we propose different scan attacks, which circumvent the security of the IC in the presence of advanced DFT techniques. We identify the limitations of our proposed scan attacks to develop countermeasures that can thwart these attacks.

Scan design is a de facto design-for-testability technique that enhances access during the manufacturing test process. However, it can also be exploited to leak secret information off a secure chip. A mode-reset countermeasure has been used to thwart all the existing scan attacks, as they all rely on switching between the test and normal modes. Recently, the countermeasure was circumvented by a new scan attack that utilizes only the test mode to identify the secret key of an AES chip. However, this test-mode-only attack has overlooked the other test structures, such as a decompressor and a compactor, on the scan path, which act as fortuitous countermeasures against test-mode-only scan attacks. In this work, we present a scan attack analysis for contemporary scan architectures with a stimulus decompressor unit. A stimulus decompressor poses a challenge for the test-mode-only attack, as the bit-flips required to launch the attack may not be created through the decompressor. The problem bears similarities to the test pattern encodability problem, where certain test cubes cannot be delivered due to the correlation induced by the stimulus decompressor. This paper sheds light to the intrinsic connections between the scan attack and the test pattern encodability problem, and presents a new test-mode-only scan attack in the presence of a decompressor of any type. Our analysis on an AES design shows that the proposed attack is successful for contemporary scan architectures. We also propose countermeasures that diminish the success of the proposed attack.

At-speed or even faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable for lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak-power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose design for testability (DfT) support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner; we develop three different DfT mechanisms, one for launch-off shift, one for launch-off capture, and one for mixed at-speed testing. The proposed DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design-flow-compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering the launch/capture power.

Design for testability (DFT) is the most common testing technique used in the modern VLSI industries. However, when this technique is incorporated in a cryptographic circuit, it may open a back door to an attacker. The attacker can get access to the internal scan chains by switching the device from the normal mode to the test mode and then observe the chip content. The scan cells which were originally used to enhance the testability, can thus be misused to access the intermediate results of the cryptographic algorithm running inside the chip. One countermeasure against such attacks is to reset the device whenever there is a switch from the normal mode to the test mode. In this work we are going to analyse this countermeasure and show that it is not completely secure against scan attack. We show that an attack is possible using only the test mode which will bypass the countermeasure.

Scan attack is a threat to crypto-chips. An attacker can leverage the test mode of the chip and control the scan chains in order to reveal the secret key. One solution for this kind of attacks is to hamper the ability to switch the device from normal mode to test mode and corrupt the data in the scan cells. If the device is reset each time it switches the mode from normal to test, all existing attacks can be thwarted. We propose a new scan-based attack by controlling only the scan chains and demonstrate it on the AES hardware. The attack uses only the test mode of the hardware and it does not require switching between normal and test mode. The attack will work even in the presence of mode blocking countermeasure. The attack requires only 375 test vectors with an attack time complexity around 212.58.

Test data compression is widely employed in scan design to tackle high test data volume (TDV) and test time problems. Given the number of scan-in pins available in automated test equipment, architectural decisions regarding the number of internal scan chains directly impact the compression level attained. While targeting an aggressive compression level by increasing the number of internal scan chains would reduce the TDV per encodable pattern, the cost of serially applying more patterns to restore the coverage loss offsets the compression benefits. Following up from our earlier work, we propose here a wide spectrum of predictive techniques for projecting the test cost of a given scan configuration for combinational xor-based decompression. The appropriate technique is selected by designers based on which stage the design is in, the design abstraction and the amount of information available, the permissible computational complexity of the techniques, and the accuracy of the projected optimal compression ratio.

At-speed or even faster-than-at-speed testing of VLSI circuits aim at a high quality screening of VLSI circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable to lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose DfT support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner. The DfT support we outline in this paper enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design flow compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering launch/capture power.

Transitions embedded in between consecutive stimulus/response bits toggle scan cells during shift operations. The consequent switching activity in the scan chains further propagate into the combinational logic, resulting in elevated power dissipation levels, and thus, endangering the reliability of the chip being tested. Based on the observation that the content of scan chains during shift operations is irrelevant and unimportant, we propose an expedited response compaction technique in order to reduce power dissipation during scan operations. Parallelized (and expedited) compaction operations help compress the entire capture response onto a single reference chain during the first portion of shift cycles, enabling a simultaneous constant-0 feed to all the remaining chains, in which no scan-out power is dissipated during the subsequent shift cycles. This DfT-based approach is nonintrusive for design flow, requires a very minor investment in area, and in turn delivers significant savings in test power. The proposed solution reduces test power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction, while retaining the observed responses intact. Experimental results justify the efficacy of the proposed technique in attaining test power reductions.

Scan architectures with compression support have remedied the test time and data volume problems of today's sizable designs. On-chip compression of responses enables the transmission of a reduced volume signature information to the ATE, delivering test data volume savings, while it engenders the challenge of retaining test quality. In particular, unknown bits (x's) in responses corrupt other response bits upon being compacted altogether, masking their observation, and hence preventing the manifestation of the fault effects they possess. In this work, we propose the design and utilization of a response compactor that can adapt to the varying density of x's in responses. In the proposed design, fan-out of scan chains to XOR trees within the compactor can be adjusted per pattern/slice so as to minimize the corruption impact of x's. Adaptiveness of the proposed response compactor enhances the observability of scan cells cost-effectively.