EDBT 2026 Demo / reviewers in the wild / expert
Kevin Casey
dblp:59/989
· DBLP profile ↗
9ranked-venue papers
3as first author
3since 2021 · last 2023
0000-0001-7245-9572ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 4 · 2 first-authorHuman-computer interaction and ubiquitous computing · 3 · 3 since 2021Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
3 papers |
Runtime systems and virtual machines · 50% Compilers and program optimization · 32% Programming languages and type systems · 18% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Runtime systems and virtual machines
interpreter design |
0.1 | 1 | 2008 | Virtual machine showdown: Stack versus registers · ACM Trans. Archit. Code Optim. 2008 |
Programming languages and type systems
method dispatch |
0.1 | 1 | 2008 | Virtual machine showdown: Stack versus registers · ACM Trans. Archit. Code Optim. 2008 |
Runtime systems and virtual machines
virtual machine architecture |
0.1 | 1 | 2008 | Virtual machine showdown: Stack versus registers · ACM Trans. Archit. Code Optim. 2008 |
Runtime systems and virtual machines › interpreter
interpreter optimization |
0.1 | 1 | 2007 | Optimizing indirect branch prediction accuracy in virtual machine interpreters · ACM Trans. Program. Lang. Syst. 2007 |
Processor architecture and microarchitecture
branch prediction |
0.1 | 1 | 2007 | Optimizing indirect branch prediction accuracy in virtual machine interpreters · ACM Trans. Program. Lang. Syst. 2007 |
Processor architecture and microarchitecture › branch prediction
branch target buffer |
0.1 | 1 | 2007 | Optimizing indirect branch prediction accuracy in virtual machine interpreters · ACM Trans. Program. Lang. Syst. 2007 |
Compilers and program optimization
code generation |
0.1 | 1 | 2006 | Fast and flexible instruction selection with on-demand tree-parsing automata · PLDI 2006 |
Compilers and program optimization › code generation
instruction selection |
0.1 | 1 | 2006 | Fast and flexible instruction selection with on-demand tree-parsing automata · PLDI 2006 |
Compilers and program optimization
register allocation |
0.0 | 1 | 2008 | Virtual machine showdown: Stack versus registers · ACM Trans. Archit. Code Optim. 2008 |
Methods — techniques the papers use, named apart from their topics
static optimization · 0.1dynamic optimization · 0.1switch dispatch · 0.1inline threading · 0.1direct threading · 0.1bytecode translation · 0.1on-demand tree-parsing automata · 0.1dynamic programming · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | A Computational Thinking Obstacle Course Based on Bebras Tasks for K-12 SchoolsabstractThis paper describes an unplugged computational thinking (CT) resource for primary and secondary schools developed from Bebras tasks. In Ireland, CT is not part of the primary school curriculum or mandatory in secondary schools. However, the National Council for Curriculum and Assessment is in the process of revising the primary school curriculum to include aspects of CT. Our aim for creating this CT Obstacle Course is to introduce teachers (and pupils) without formal computer science training to the subject of CT. This is done in a manner that informs and motivates, and gives them the confidence to deliver CT materials in the classroom. We also want to find out from teachers how useful and important this type of resource is for developing problem-solving skills, and if our unplugged activity can support learning at various skill levels. Our CT Obstacle Course includes 14 Bebras tasks for primary schools and an additional 6 Bebras tasks for secondary schools. The activity is suitable for indoors and outdoors and is completed in groups, promoting teamwork and communication. We have delivered it to 146 primary school classes during 38 school visits between May 2021 and June 2022. It has been undertaken by 3,445 pupils and 195 teachers and other school staff. This paper describes our CT resource in detail, and reports teacher feedback from primary schools. Taina Lehtimäki, Rosemary Monahan, Aidan Mooney, Kevin Casey, Thomas J. Naughton |
ITiCSE (1) | 4 |
| 2023 | Computational Thinking Resources Inspired by BebrasabstractIn this poster, we highlight computational thinking resources for schools from the PACT team at Maynooth University, Ireland. The resources are derived from tasks from the Bebras international computational thinking initiative. The different modalities work together throughout the school year to provide initial exposure to computational thinking, and include an obstacle course, seasonal tasks, and a workbook. Taina Lehtimäki, Rosemary Monahan, Aidan Mooney, Kevin Casey, Thomas J. Naughton |
ITiCSE (2) | 4 |
| 2022 | Bebras-inspired Computational Thinking Primary School Resources Co-created by Computer Science Academics and TeachersabstractThis paper describes our process of creating computational thinking (CT) resources for primary school teachers in Ireland. The National Council for Curriculum and Assessment has proposed a revised primary mathematics curriculum with an emphasis on CT skills and problem solving, and some teachers would like to introduce it already on an informal basis. However, CT is not yet part of teacher training. Our motivating question has been: how can teachers without a computer science background deliver CT at primary level in Ireland? Our process involves third-level computer science academics co-creating resources with in-service and pre-service teachers during workshops. The resources comprise a workbook and lesson plans. Our resources are based on tasks from the International Bebras Challenge, a well-known large-scale international CT contest with a reasonably gender-neutral profile of school-age participants. The workbook consists of ten Bebras tasks, each followed by a page of original activities on the theme of the task. A set of ten lesson plans accompanies the workbook. Each lesson plan has information about how to use the corresponding workbook activities in the classroom, where the activity might fit into the existing curriculum, categorisation of the task in terms of eight CT topics, differentiation, and extension activities. This paper explains our process of workshop planning, workbook creation, and lesson plan co-creation. Preliminary evaluation of our process uses teacher feedback. Taina Lehtimäki, Rosemary Monahan, Aidan Mooney, Kevin Casey, Thomas J. Naughton |
ITiCSE (1) | 4 |
| 2008 | Virtual machine showdown: Stack versus registersabstractVirtual machines (VMs) enable the distribution of programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the design of VMs is whether a stack architecture or register architecture can be implemented more efficiently with an interpreter. We extend existing work on comparing virtual stack and virtual register architectures in three ways. First, our translation from stack to register code and optimization are much more sophisticated. The result is that we eliminate an average of more than 46% of executed VM instructions, with the bytecode size of the register machine being only 26% larger than that of the corresponding stack one. Second, we present a fully functional virtual-register implementation of the Java virtual machine (JVM), which supports Intel, AMD64, PowerPC and Alpha processors. This register VM supports inline-threaded, direct-threaded, token-threaded, and switch dispatch. Third, we present experimental results on a range of additional optimizations such as register allocation and elimination of redundant heap loads. On the AMD64 architecture the register machine using switch dispatch achieves an average speedup of 1.48 over the corresponding stack machine. Even using the more efficient inline-threaded dispatch, the register VM achieves a speedup of 1.15 over the equivalent stack-based VM. Yunhe Shi, Kevin Casey, M. Anton Ertl, David Gregg |
ACM Trans. Archit. Code Optim. | 2 |
| 2007 | Optimizing indirect branch prediction accuracy in virtual machine interpretersabstractInterpreters designed for efficiency execute a huge number of indirect branches and can spend more than half of the execution time in indirect branch mispredictions. Branch target buffers (BTBs) are the most widely available form of indirect branch prediction; however, their prediction accuracy for existing interpreters is only 2%--50%. In this article we investigate two methods for improving the prediction accuracy of BTBs for interpreters: replicating virtual machine (VM) instructions and combining sequences of VM instructions into superinstructions. We investigate static (interpreter build-time) and dynamic (interpreter runtime) variants of these techniques and compare them and several combinations of these techniques. To show their generality, we have implemented these optimizations in VMs for both Java and Forth. These techniques can eliminate nearly all of the dispatch branch mispredictions, and have other benefits, resulting in speedups by a factor of up to 4.55 over efficient threaded-code interpreters, and speedups by a factor of up to 1.34 over techniques relying on dynamic superinstructions alone. Kevin Casey, M. Anton Ertl, David Gregg |
ACM Trans. Program. Lang. Syst. | 1 |
| 2006 | Fast and flexible instruction selection with on-demand tree-parsing automataabstractTree parsing as supported by code generator generators like BEG, burg, iburg, lburg and ml-burg is a popular instruction selection method. There are two existing approaches for implementing tree parsing: dynamic programming, and tree-parsing automata; each approach has its advantages and disadvantages. We propose a new implementation approach that combines the advantages of both existing approaches: we start out with dynamic programming at compile time, but at every step we generate a state for a tree-parsing automaton, which is used the next time a tree matching the state is found, turning the instruction selector into a fast tree-parsing automaton. We have implemented this approach in the Gforth code generator. The implementation required little effort and reduced the startup time of Gforth by up to a factor of 2.5. M. Anton Ertl, Kevin Casey, David Gregg |
PLDI | 2 |
| 2005 | Tiger - An Interpreter Generation Tool
Kevin Casey, David Gregg, M. Anton Ertl |
CC | 1 |
| 2005 | The case for virtual register machines
David Gregg, Andrew Beatty, Kevin Casey, Andy Nisbet |
Sci. Comput. Program. | 3 |
| 2003 | Towards Superinstructions for Java Interpreters
Kevin Casey, David Gregg, M. Anton Ertl, Andy Nisbet |
SCOPES | 1 |