Demo Data from EDBT 2026 / reviewers in the wild / expert
Kevin Macdonald
dblp:59/9943
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › simulation › architectural simulation
full-system simulation |
0.2 | 1 | 2014 | PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks · IEEE Trans. Computers 2014 |
Performance modeling and evaluation › simulation › communication system simulation
network simulation |
0.2 | 1 | 2014 | PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks · IEEE Trans. Computers 2014 |
Performance modeling and evaluation
simulation |
0.2 | 1 | 2014 | PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks · IEEE Trans. Computers 2014 |
Performance modeling and evaluation › simulation › discrete-event simulation
trace-driven simulation |
0.2 | 1 | 2014 | PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks · IEEE Trans. Computers 2014 |
Methods — techniques the papers use, named apart from their topics
trace-based simulation · 0.2dependency inference · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip NetworksabstractWith the advent of large scale chip multiprocessors, there is growing interest in the design and analysis of on-chip networks. Full-system simulation is the most accurate way to perform such an analysis, but unfortunately it is very slow and thus limits design space exploration. To overcome this problem researchers frequently use trace-based simulation to study different network topologies and properties, which can be done much faster. Unfortunately, unless the traces that are used include information about dependencies between packets, trace-based simulations can lead one to draw incorrect conclusions about network performance metrics such as average packet latency and overall execution time. The primary contributions of this work are to demonstrate the importance of including dependency information in traces, and to present PDG_GEN, an inference-based technique for identifying and including dependencies in traces. This technique uses traces obtained from multiple full-system simulations of an application of interest to infer dependency information between packets and augment traces with this information. On the SPLASH-2 benchmark suite, PDG_GEN is 2.3 times more accurate at predicting overall execution time and almost 4,000 times more accurate at predicting average packet latency than traditional trace-based methods. Kevin Macdonald, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella |
IEEE Trans. Computers | 1 |
| 2011 | Inferring packet dependencies to improve trace based simulation of on-chip networksabstractWith the advent of large scale chip-level multiprocessors, there is a growing interest in the design and analysis of on-chip networks. The use of full system simulation is the most accurate way to perform such an analysis, but unfortunately it is very slow and thus limits design space exploration. In order to overcome this problem researchers frequently use trace based simulation to study different network topologies and properties, which can be done much faster. Unfortunately, unless the traces that are used include information about dependencies between messages (packets), trace based simulation can lead one to draw incorrect conclusions about network performance metrics such as latency and overall execution time. In this paper we will demonstrate the importance of including dependency information in traces, as well as present an inference-based technique for identifying and including dependencies, and show that using these augmented traces results in much better simulation accuracy without excessively extending simulation time. Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella |
NOCS | 2 |