Privacy-preserving k-nearest neighbor (PPkNN) classification for multiple clouds enables categorizing queried data into a class in keeping with data privacy, where the database and key servers jointly perform cryptographic operations. The existing solutions, unfortunately, take a long time and incur a large amount of traffic between the database and key servers. Therefore, in this paper, we propose a fast and secure kNN classification protocol, namely FSkNN, over distributed databases deployed in multiple clouds under the semi-honest model. Particularly, we focus on optimizing the network-related operations during kNN classification. That is, the proposed cryptographic protocol reduces the number of interactions between the servers by using a fully homomorphic encryption scheme and eliminates unnecessary traffic by applying mathematical techniques. In addition, the indistinguishability-based security of FSkNN is proven. We implemented FSkNN with C++ and the testbed experiments demonstrate that the proposed scheme significantly facilitates the query response time and reduces the communication cost.

Classification of wafer map defect patterns is important to monitor occurrence and further to assist root cause analysis of manufacturing-process-induced systematic defects. CapsNet, a variant of convolutional neural network, contains a decoder network which tries to reconstruct an input image, and during training loss function is calculated not only for prediction error but also for difference between reconstructed and input images. Improving the quality of reconstructed image might lead to improvements on prediction capability. It would also assist root-cause analysis of systematic defects, since not only category but also locations and shapes for the predicted systematic defect are more clearly reported. In this paper we report on our improvements on reconstruction capability of CapsNet-based wafer map defect pattern classifier. Mainly targeting scratch defect pattern, we tuned network architecture of the classifier. We generated a synthesized high-resolution wafer map dataset, and applied a mixture of sub-categories as training data in order to improve reconstruction capability even under appearances of noises on a wafer and chopped curves. We also propose a set of measures to evaluate quality of a reconstructed defect pattern images.

Classification of wafer map defect patterns is important to monitor occurrence and further to assist root cause analysis of manufacturing-process-induced systematic defects. In this study we develop CapsNet-based wafer map defect pattern classifier. CapsNet is a variant of convolutional neural network, which extract features of images as vectors, not as scalars, and is expected to extract features more accurately under fluctuations of locations, angles, and scales of features in input images. Experimental results indicate that, by combining 2-stage (detector and classifier) approach, the proposed scheme shows higher accuracy on WM-811K real wafer map dataset for 8 categories in comparison to the previous work, on average and especially on the categories “Donut” and “Scratch,” which are difficult to accurately categorize by the previous work.

Mobile crowdsourcing outsources large-scale tasks to a crowd of mobile users. To efficiently perform such tasks, many studies on tasks assignment have been conducted. However, the existing task assignment algorithms assume that each task can be completed by single worker. In reality, there are many types of tasks, including disaster recovery, which must be processed by multiple workers. To tackle this issue, we first introduce the problem of collaborative-task assignment, where multiple workers must collaborate to perform each task. To the best of our knowledge, this paper is the first work that address such a problem. Then, we propose a collaborative-task assignment (CTA) algorithm to efficiently complete a set of collaborative tasks by minimizing the idle times of workers. The simulation results using the real mobility traces as well as random graphs demonstrate that the proposed CTA algorithm achieves its design goals.

Mobile crowdsourcing in opportunistic networks outsources location-based tasks, such as taking photos and surveying Wi-Fi signal characteristic at points of interests, to a crowd of workers. The performance of tasks assignment is generally evaluated by the makespan. However, not only the makespan, but also the quality of performed tasks is important. Therefore, in this paper, we propose two task assignment schemes. One is the quality-aware task assignment (QA-TA) that tries to maximize the quality of tasks for given a deadline; the other is the minimum quality threshold task assignment (MQT-TA) that tries to minimize the makespan for a given minimum quality requirement. To this end, we apply the optimal stopping, which is one of the widely used techniques in mathematics, to the algorithm designs. The simulations using real mobility traces demonstrates that the proposed schemes successfully achieve their design goals.

Delay tolerant networks (DTNs) are widely adopted to many network applications, such as disaster recovery and battlefield communications. Such critical network scenarios call for an outright prevention mechanism against contact-based attacks, e.g., blackmailing a legitimate user to compromise sensitive information at a contact. To the best of our knowledge, there is no work on secure routing protocol against contact-based attacks in DTNs. Therefore, in this paper, we first formulate the problem of contact avoidance routing, in which the node holding a message tries to avoid having a contact with an adversary. By applying the phase-type distribution, we build the secure opportunistic path model, which integrates the delivery probability within the deadline and the safety of opportunistic paths. Then, we propose a contact avoidance routing (CAR) protocol to securely deliver a message to its destination against the contact-based compromise attack. In addition, we further propose an adaptive CAR (A-CAR) to accommodate complicated network scenarios, where the capabilities of adversaries are parameterized. The extensive simulations using real traces as well as random graphs demonstrate that the proposed CAR and A-CAR protocols achieve their design goals.

For electric vehicles and hybrid vehicles in recent years, there has been a significant increase in the costs of implementing EMC technology to protect Controller Area Networks (CANs) from the influence of switching noise from power converter circuits. In this paper, we have investigated a method that aims to work with EMC in the future, from the perspective of dependable computing technology, to reduce its costs. Here, we define a fault model based on an experiment in which noise emitted from the DC-DC converter was applied to a CAN bus, and propose an application layer-based hybrid communications protocol consisting of an Automatic Repeat reQuest (ARQ), Forward Error Correction (FEC), and HALT mode. In this protocol, there is a transition to a suitable mode by reference to send/receive error counters incorporated in the CAN node. In an experiment in which noise was applied to a CAN node using simulated noise application circuits, we measured the total number of overhead frames and non-utilization rate, and we demonstrate the benefit of the proposed protocol in terms of increased fault tolerance when sending data frames in a highly electromagnetic environment.

Software rejuvenation is a technique to prevent the aging of running software. Recently, benefits of software rejuvenation in high-performance computing (HPC) areas have received attention. In time warp-based parallel discrete event simulation (PDES) systems, it is important to improve performance to equalize simulation progress in processes. In this article, we consider a number of schemes for time warp-based PDES to avoid the imbalance simulation progress introduced by rejuvenation.

This paper focuses on FPGA for realtime applications and proposes a redundant configuration scheme with rejuvenation on a dual-FPGA architecture to handle SEUs. Duplication check is utilized to detect errors within the FPGAs. Rollback and re-computation will be attempted when the error is detected. If the error remains, the rejuvenation will be triggered. The proposed architecture consists of two identical FPGAs. When one FPGA has to undergo a rejuvenation process, the other will be available to operate the system. This ensures the real time computing constraint of an application.

In this study we discuss fault tolerant routing mechanism for the P2P network, Chord, considering the existence of faulty or malicious nodes. We propose a routing protocol which works despite existence of faulty nodes. We modify the original Chord routing protocol so that it can handle redundant lookups of multiple "knuckles," and replica or data fragments allocation on knuckles. Analysis based on mathematical models and simulations show that the proposed protocol effectively avoids the interruption of object supply caused by the target node fault and/or the acquisition failure of objects caused by malicious nodes tampering.

Recently, a microcomputer and a FPGA are apt to be used for control of the power conversion circuits because of their capability to simplify the parameter resetting and also their flexibility on the basis of programming by software. On the other hand, the control circuits are getting extremely close to the high current main circuit. Thus the electro-magnetic radiation generated nearby the high current pulse may affect the control circuit as transient faults. In this study, we focus on transient noise caused by switching activities of a DC-DC converter and propose a dependable digital power control circuit by FPGA. The basic idea is to keep the sampling times as far away from the switching times as possible to avoid the effects of transient noise. A control circuit, with the proposed method applied, is designed and its effectiveness is shown by simulations.

In recent electronic vehicles (EVs) and hybrid vehicles (HVs), there are growing concerns about electromagnetic interference (EMI) caused by significantly-high voltage switching in DC-DC converters. The most remarkable characteristic of the coverter noise is in its periodicity. In this article, a noise injection experiment to a controller area network (CAN) bus by using a DC-DC converter is presented. Dispite the switching period of the converter was much shorter than the time length of a data frame transmission, we found that the switching did not always cause CAN errors. On the basis of this observation, we discuss characteristics of the converter noise and some basic ideas for improving the immunity of CAN networks against the converter noise by using dependable computing techniques.

This paper releases a report of the application for the fault tolerant sequential circuit technique against periodical transient faults under highly electromagnetic environment. After implementing the proposed fault tolerant technique on a counter in our previous paper, as an example of how the proposed architecture performs on utility-scale sequential circuits, the result obtained by applying the technique to a processor is illustrated. On the basis of our logic simulation, we confirm that the originally designed 8-bit processor with functional BIST can avoid the periodical multiple transient faults. We further show that sequential circuits with a practical size of a processor can apply the fault tolerant technique with low overhead from the viewpoint of the circuit space.

Some cloud storage services have recently introduced file versioning features by which more than one version of a file can be maintained. For providing file versioning with limited storage resources, it is essential to divide the resources among versions in accordance with the varied needs of numerous users. In this paper, we focus on applications in which newer versions of a file are more likely to be requested, which may be true in the case of many subscription services. We propose a new distributed data replication protocol supporting the file versioning feature. We also construct an analytical model that can derive an optimal allocation of the resources when the total number of replica nodes in a system and the distribution of the frequency of read requests for each version are given. In addition, we present some numerical examples obtained by simulations to show the good scalability and dependability of our system by assuming some realistic parameters.

Convolutional compactors offer a promising technique of compacting test responses. In this study the authors expand the architecture of convolutional compactor onto a Galois field in order to improve compaction ratio as well as reduce X-masking probability, namely, the probability that an error is masked by unknown values. While each scan chain is independently connected by EOR gates in the conventional arrangement, the proposed scheme treats q signals as an element over GF (2q), and the connections are configured on the same field. The authors show the arrangement of the proposed compactors and the equivalent expression over GF (2). The authors then evaluate the effectiveness of the proposed expansion in terms of X-masking probability by simulations with uniform distribution of X-values, as well as reduction of hardware overheads. Furthermore, the authors evaluate a multi-weight arrangement of the proposed compactors for non-uniform X distributions

The authors have developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. The scheme achieved a 100times compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, the masking logic was enhanced to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. The scheme was applied to five real VLSI chips, and the technique compressed the test data by 100times for scan-based BIST

Maintaining the replicated data between nodes can improve the dependability of data. We propose a probabilistic trapezoid protocol for replicated data that combines this protocol with the concept of a probabilistic quorum system. We analyzed read availability, the latest version read availability and the average number of nodes accessed for the protocol. Our numerical evaluations demonstrated that it improves not only read availability but also latest version read availability. Furthermore, when the number of nodes is greater than 100, it could effectively reduce system load. We designed and implemented a file transfer protocol to replicate data. Experimental results proved that the trapezoid protocol could achieve better throughput than quorum system or grid protocol. Despite node failure, the probabilistic trapezoid protocol also achieved relatively better throughput.

Convolutional compactors offer a promising technique of compacting test responses that include unknown values. One drawback of this compaction technique is error masking, i.e., some errors appearing in the test responses cannot be detected due to mutual cancellation. In this work, we theoretically analyze error-masking probability. First, we apply weight distributions of binary linear error-correcting codes to derive the error-masking probability. We then present a fast calculation scheme for 4- and 6-error-masking probabilities. Numerical examples reveal that they are about the same as those obtained by Monte-Carlo simulations. We also analyze X-masking probability, that is, the probability that an error is masked by unknown values. We present tree-search-based calculation, as well as approximated value

In this paper, we discuss the application of a seed-selection procedure for LFSR-based BIST to multiple scan chains, combined with a phase shifter. We introduced the procedures for selecting seeds and arrangement of phase shifters under the restriction of limiting additional hardware overheads, and evaluated them in respect to the number of test patterns required to achieve 100% fault coverage. Experimental results shows that that the test length was reduced in comparison with cases in which phase shifters or seed-selection procedures were not applied, under condition where the number of EOR gates in the phase shifter were restricted.

Replicating data is a promising way of improving the dependability of large distributed systems. The hybrid data replication protocol combines concepts of the tree quorum protocol and grid protocol. We present an analytical evaluation of read/write availability for the generalized hybrid data replication protocol, which extends the arrangement of nodes into a more general form to improve write availability. The average number of nodes accessed for read/write operations is also analyzed under the assumption that nodes might fail. Equations are derived based on node availability p, and numerical examples are shown. We use computer simulations to estimate the throughput for read/write operations.

We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over GF(2m), where m is the number of LFSR stages. The results indicate that test lengths derived through selected seeds are about sixty percent shorter than those derived by conventionally selected seeds for a given fault coverage. We also show that seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In terms of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.

A scheme for testing SRAMs is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurable cells required for the tester circuit. We then propose a tester for a 4 Mbit SRAM with reconfigurable cells of 16 bit data SRAMs. We also report the implementation of the proposed circuit. Four 16 bit reconfigurable cells, each of which consists of an SRAM and two CPLDs, were implemented, and mounted on a board. We confirmed that the tester functions correctly by performing a marching test.

In this paper we evaluate the effectiveness of using convolutional codes under a time limit for recovery as a method for packet loss recovery. We analyze the method's operation when a limitation on the number of received packets is substituted for the time limitation, and derive the probability for a lost packet being recovered before the arrival of the limiting number of succeeding packets. We also evaluate this probability in the results of simulation and estimate the buffer size required for a decoder. Moreover we apply this method in constructing a dependable videoconference system and observe the resulting improvement in QoS.

Developed a partially rotational scan (PRS) register used for the n-detection BIST (built-in self-test) that can detect not only delay faults but also unmodeled faults. The developed circuit consists of a shift register with partial rotation. Also presents a procedure for selecting test vectors from ATPG (automatic test pattern generation) ones. This testing method enables at-speed testing and the stuck-at fault coverage of n/spl times/100% by using subset of the ATPG vectors. And it drastically reduces the number of vectors input from an external low-speed tester. Computer simulations of stuck-at fault coverage are conducted on ISCAS'85, ISCAS'89, and ITC'99 circuits for detection times n of 1, 2, 3, 5, 10, and 15. They show that the compaction rates of the ATPG test vectors range from 52.4% (s713) to 0.9% (c499) of origin. This result demonstrates that the PRS register can accomplish low-cost, at-speed testing.

The ability of convolutional-code-based FEC to recover from packet losses over a channel subjected to burst erasure is evaluated. We analyze the maximum lengths of a burst packet loss that can be recovered. We assume that only one burst packet loss has occurred, and consider the recovery conditions for given lengths, that is, numbers of lost packets. We also present conditions for the generator matrices, which are used to encode and decode convolutional-code-based redundant packets. We then apply a packet loss model based on a two-state Markov chain and use computer simulation to examine the ability of our approach to recover packets lost in transmission over bursty erasure channels. We show that this ability changes with the constraint length of the applied code and with the generator matrix, and find conditions for a matrix to have high levels of ability. Finally, we apply our method to the transfer of graphic data over the Internet, and use convolutional codes in the recovery process.