We present HipHop.js, a synchronous reactive language that adds synchronous concurrency and preemption to JavaScript. Inspired from Esterel, HipHop.js simplifies the programming of non-trivial temporal behaviors as found in complex web interfaces or IoT controllers and the cooperation between synchronous and asynchronous activities. HipHop.js is compiled into plain sequential JavaScript and executes on unmodified runtime environments. We use three examples to present and discuss HipHop.js: a simple web login form to introduce the language and show how it differs from JavaScript, and two real life examples, a medical prescription pillbox and an interactive music system that show why concurrency and preemption help programming such temporal applications.

In the 20th century, an embedded system was most often thought of as a single piece of equipment driven by a single software program. Many efficient modeling, programming and verification paradigms have been developed in this setting: mathematical modeling using differential equations, reactive and synchronous programming, data-flow based signal processing, model-checking, etc. In the 21st century, systems are becoming much more complex. They mix hardware and software in subtle ways, involve a large number of sensors and actuators, become physically distributed, and may be remotely controlled by Web-based devices such as smartphones. Designing and verifying such systems raises many challenges that were independently known in particular areas but now need to be solved together. Here are some: understanding the relation between continuous and discrete time models, still quite unclear in the available mathematical modelers; understanding the ways in which synchronous and asynchronous communication could work in harmony; relaxing determinacy and timing constraints without losing too much predictability; being able to write full and faithful simulators of systems before building them, which is still a big problem in areas such as SoCs or transportation networks; developing methods to couple classical embedded systems with Web-based systems, which are of a very different nature. We will review some of the new problems posed in this area and some emerging solutions that could be applied to them, taking the notion of causality as the pivot of our reflections.

Do formal verification tools and methodologies require a drastic overhaul to move beyond equivalence checking? Equivalence checking catches errors in synthesis and local hand-modifications to designs. However, powerful formal verification technologies are emerging to combat "behavioral" errors, which represent today's biggest verification problems. Nonetheless, formal verification experts are split on how formal tools should adapt to this challenge. Some of our panelists feel that designers can sufficiently benefit from new formal verification technologies by making incremental changes to current methodologies. Others, however, argue that major changes are required to reap meaningful benefits from these new technologies. Just how much change is enough, what is the capacity of our current tools and what is limiting the full deployment of FV technology.Our panel of experts, consisting of users, tool providers, and core engine builders, will answer these challenging questions. The panel will debate these issues while discussing real life examples from the user base. They will provide a perspective of how the progression of technology will bring the real promise of formal verification to the user base.

The focus of this panel is on issues surrounding the use of C++ in modeling, integration of silicon IP and system-on-chip designs. In the last two years there have been several announcements promoting C++ based solutions and of multiple consortia (SystemC, Cynapps, Accellera, SpecC) that represent increasing commercial interest both from tool vendors as well as perhaps expression of genuine needs from the design houses. There are, however, serious questions about what value proposition does a C++ based design methodology bring to the IC or system designer? What has changed in the modeling technology (and/or available tools) that gives a new capability? Is synthesis the right target? or VAlidation? Tester modeling or testbench generation? This panel brings together advocates and opponents from the user community to highlight the achievements and the challenges that remain in use C++ for use in microelectronic circuits and systems.

Controller circuits synthesized from high-level languagesoften have many more latches than the minimum,with a resulting sparse reachable state space thathas a particular structure. We propose an algorithmthatexploits this structure to remove latches. The reachablestate set (RSS) is much easier to compute for the new,smaller circuit and can be used to efficiently computethe RSS of the original. Thus we provide a method forobtaining the RSS, and two different initial implementationsfrom which to begin logic optimization.

In a gate-level description of a finite state machine (FSM), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.

We present a new programming paradigm called Communicating Reactive Processes or CRP that unifies the capabilities of asynchronous and synchronous concurrent programming languages. Asynchronous languages such as CSP, Occam, or Ada are well-suited for distributed algorithms; their processes are loosely coupled and communication takes time. The Esterel synchronous language is dedicated to reactive systems; its processes are tightly coupled and deterministic, communication being realized by instantaneous broadcasting. Complex applications such as process or robot control require to couple both forms of concurrency, which is the object of CRP. A CRP program consists of independent locally reactive Esterel nodes that communicate with each other by CSP rendezvous. CRP faithfully extends both Esterel and CSP and adds new possibilities such as precise local watchdogs on rendezvous. We present the design of CRP, its semantics, a translation into classical process calculi for program verificatio...

We introduce a new kind of abstract machine based on the chemical metaphor used in the Γ language of Banâtre & al. States of a machine are chemical solutions where floating molecules can interact according to reaction rules. Solutions can be stratified by encapsulating subsolutions within membranes that force reactions to occur locally. We illustrate the use of this model by describing the operational semantics of the TCCS and CCS process calculi. We also show how to extract a higher-order concurrent λ-calculus out of the basic concepts of the chemical abstract machine.

Vufllemm's results on opumal computations of recurswe programs are generalized New syntactic results are obtained by considering spaces of denvauons instead of terms The results apply to classes of mterpretauons more general than the sequential interpretations of Vmllemm

Procedure call mechanisms have mainly been studied in the framework of recursive programs without assignments, for the simplicity of their operational and denotational semantics (See Scott [16], Nivat [14], Vuillemin [17]).