EDBT 2026 Demo / reviewers in the wild / expert
Sherin Kuriakose
dblp:60/1522
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware test |
0.1 | 1 | 2006 | InTeRail: A Test Architecture for Core-Based SOCs · IEEE Trans. Computers 2006 |
Electronic design automation › hardware verification and test
system-on-chip testing |
0.1 | 1 | 2006 | InTeRail: A Test Architecture for Core-Based SOCs · IEEE Trans. Computers 2006 |
Electronic design automation › hardware verification and test › design for testability
test access mechanism |
0.1 | 1 | 2006 | InTeRail: A Test Architecture for Core-Based SOCs · IEEE Trans. Computers 2006 |
Electronic design automation › hardware verification and test › system-on-chip testing
embedded core testing |
0.0 | 1 | 2006 | InTeRail: A Test Architecture for Core-Based SOCs · IEEE Trans. Computers 2006 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | InTeRail: A Test Architecture for Core-Based SOCsabstractA flexible test architecture for embedded cores and all interconnects in a system-on chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM paths. It also provides for dynamic wrapper reconfiguration. Algorithms that minimize the use of extra interconnects for the TAM path formation are presented and evaluated. Dimitrios Kagaris, Spyros Tragoudas, Sherin Kuriakose |
IEEE Trans. Computers | 3 |