The processing-using-memory (PUM; a.k.a. inmemory computing) paradigm aims to eliminate data movement energy and performance costs by using memory cell interactions to directly perform computation. Given PUM's potential for large savings, prior works have proposed many different datapath microarchitectures to demonstrate how general-purpose PUM benefits a wide range of application kernels. Unfortunately, these efforts largely depend on microarchitecture-specific vector-like interfaces that (1) force many of an application's operations to be offloaded to a CPU, (2) require significant programmer effort to scale up applications to an entire memory chip, and (3) make it impractical to develop badly-needed systems software and programming tools for PUM. To address these three issues, we propose the memory processing unit (MPU), a microarchitecture-agnostic interface layer for general-purpose PUM with three components. First, we develop an MPU instruction set architecture (ISA) with instructions to facilitate application scaling and task coordination. Second, we propose an ensemble execution model that coordinates execution across millions of PUM vector function units and maps to most general-purpose PUM microarchitectures. Third, we design a comprehensive MPU control path that efficiently executes MPU ISA binaries across multiple ensembles, and can enable CPU-free execution of complex end-to-end applications with PUM. We demonstrate how the MPU maps to multiple previously-proposed PUM datapaths, and how it achieves average performance/energy improvements of$\mathbf{1. 7 9} \times \boldsymbol{/} \mathbf{3. 2 3} \times$for$\mathbf{2 1}$data-intensive kernels over these prior works ($67 \times / 47 \times$vs. a modern GPU), while also achieving performance and energy improvements for the complex end-to-end applications.

To combat the high energy costs of moving data between main memory and the CPU, recent works have proposed to perform processing-using-memory (PUM), a type of processing-in-memory where operations are performed on data in situ (i.e., right at the memory cells holding the data). Several common and emerging memory technologies offer the ability to perform bitwise Boolean primitive functions by having interconnected cells interact with each other, eliminating the need to use discrete CMOS compute units for several common operations. Recent PUM architectures extend upon these Boolean primitives to perform bit-serial computation using memory. Unfortunately, several practical limitations of the underlying memory devices restrict how large emerging memory arrays can be, which hinders the ability of conventional bit-serial computation approaches to deliver high performance in addition to large energy savings.

We propose locally rewritable codes (LWC) for resistive memories inspired by locally repairable codes (LRC) for distributed storage systems. Small values of repair locality of LRC enable fast repair of a single failed node since the lost data in the failed node can be recovered by accessing only a small fraction of other nodes. By using rewriting locality, LWC can improve endurance and power consumption which are major challenges for resistive memories. We point out the duality between LRC and LWC, which indicates that existing construction methods of LRC can be applied to construct LWC.

Resistive memories, such as phase change memories and resistive random access memories, have attracted significant research interest because of their scalability, non-volatility, fast speed, and rewritability. However, their write endurance needs to be improved substantially for large-scale deployment of resistive memories. In addition, their write power consumption is much higher than the power consumption of read operation. Inspired by locally repairable codes (LRCs) recently introduced for distributed storage systems, we propose locally rewritable codes (LWCs) for resistive memories. We define a novel parameter ofrewriting locality, which can be connected torepair localityof LRC. As small values of repair locality of LRC enable fast repair in distributed storage systems, small values of rewriting locality of LWC are able to reduce the problems of write endurance and write power consumption. We show how a small value of rewriting locality can improve write endurance and power consumption by deriving the upper bounds on writing cost. Also, we point out the dual relation of LRC and LWC, which indicates that the existing construction methods of LRC can be applied to construct LWC. Finally, we investigate the construction of LWC with error correcting capability for random errors.

In this paper, we present a vision for the cointegration of deeply scaled complementary metal-oxide-semiconductor (CMOS) and emerging nanoelectronic devices into CMOS-hybrid systems. These hybrid systems will create new functionality, modality and add value to existing CMOS integrated circuits. We describe several new nanoelectronic devices which may enable new dimensions to traditional CMOS circuits and systems that build on CMOS compatible, parallel nanoscale fabrication methods. In addition, we show that the integration of multimodal sensors and nonvolatile memory enables a platform of self-evolving hardware that is able to adapt to fabrication variation, environmental changes, and applications changes on-the-fly.

In bit-patterned media (BPM) aimed at magnetic recording densities of 1 Tbit/in2and higher, adjacent tracks may become very close leading to significant inter-track interference (ITI). Read-head offset or track mis-registration (TMR) can further degrade the performance of the channel. To investigate the effects of ITI and TMR on the performance of the channel, we have developed a two-dimensional (2D) pulse response simulator for BPM. Simulation results using these pulse responses suggest that equalizers and detectors optimized for zero TMR may not perform well in the presence of TMR. To mitigate the effects of TMR, we propose a modified trellis for the Viterbi algorithm (VA). The modified VA (MVA) takes into account the ITI while computing branch metrics. Simulation results show that the MVA can improve the bit error rate in the presence of TMR.

In disk forensics application, the goal is to determine whether a particular floppy disk was recorded in a particular drive. This paper discusses how image processing is used to determine whether a disk was recorded in drive A or drive B. Microscope images of floppy disk surfaces are used to extract features. Each image exhibits tracks and gaps as parallel shallow arcs, and the track and gap widths are extracted as features. We apply an image processing method to the shallow arcs to extract their widths. The Hough transform (PVC Hough, 1962) and the concept of entropy are used to segment each arc, and a simple and unbiased parabola fitting is used to fit a circle to the arc segment. Results show this method extracts track and gap widths of real images successfully resulting in the two floppy drives being distinguishable.

Dropouts are intermittent losses of signal commonly seen in magnetic tape recording readout. The main reason for such losses is the increased spacing between the head and the medium due to media defects or debris particles. The resulting signal is not only degraded by the apparent amplitude loss, but the characteristics of the pulses due to transitions are also changed. Moreover, in many cases, the locations of the pulses are altered, causing excessive amounts of peakshift. In this paper, a model, linking the liftoff to these effects, is presented. Experimental verification of the model using actual signals from a test tape drive is also given. Artificial dropout waveforms generated using this model are used to test two different read channel strategies. The first approach is an equalization-based correction scheme that attempts to undo the dropout. Results indicate that the dropout effects can be almost completely eliminated if an appropriate equalization procedure is applied. As an alternative approach, it is shown that the use of turbo coding in the presence of dropouts appears to be promising.

We consider the issue of combating signal dropouts in magnetic tape recording. Dropouts are a major limiting factor in the performance of the channel as they cause long bursts of bit errors. To attack this problem, a model of the dropout event has been developed. Based on that model, a strategy has been identified in which an envelope detector followed by a feedforward equalizer is used. The equalization process is done in such a way as to address the three major effects caused by a dropout event: amplitude loss, pulse widening and peakshift. The crucial part of this scheme is the spacing profile estimator, which makes use of an envelope detector. With this scheme, the effects of the dropout are corrected at the expense of a delay in the channel. The model of the dropout and the correction scheme are all presented.