Practice has shown that programming a new multicore system is a greater challenge than previously thought. The challenge is to produce the resulting system in a way, which is as easy as sequential programming. This new trend has changed the way we think about the whole development process. The aim of this work is to show that it is possible to develop a multicore embedded system application using existing tools, while at the same time, obtaining reuse. This process is carried out in a cyclic and increasing manner, generating a more refined version of the application at each iteration. The development process consists of five phases: Multitask Modelling, Code Generation, Test/Debugging, Mapping Tasks to Cores and Tuning the Application. The three initial ones are carried out using the Visual RTXC tool, whereas the last two use the performance tool TAU. Using a small application, a Case Study shows how the proposed development process works and the steps involved in the implementation of an embedded system.

Image processing applications are well established in modern society, presenting continuous advances and challenges. One of its fundamental techniques is morphological image processing, a nonlinear branch in image processing, which have high performance requirements. Although usually demanding for general purpose processors, it presents a high degree of achievable parallelism, making FPGA based platforms suitable candidates for this task. However, ad-hoc FPGA implementations of specialized functions to be applied to images of varying dimensions suffers from long development times and lack of flexibility. In the literature, several intelligent systems using mathematical morphology were proposed for image processing tasks, where their main bottleneck is to evaluate the fitness function for image training pairs. In this context usually sets of low spatial resolution image pairs for the training process are used. However, the fitness evaluation timing for those problems is very demanding in practice. The scheme presented in this paper aims to tackle these limitations, proposing a strategy to automatically generate custom parallel processors for morphological image processing. The proposed scheme consists of a general architecture, and a software tool used to generate custom processors. The scheme is implemented using Matlab, which generates synthesizable Verilog structures based on a few textual parameters of morphological operations and image dimensions. Experimental results have shown the method effectiveness, generating custom processors capable to perform morphological transformations on images.

This paper describes an alternative approach to direct mapping loops described in high-level languages onto FPGAs. Different from other approaches, this technique does not inherit from software pipelining techniques. The control is distributed over operations, thus a finite state machine is not necessary to control the order of operations, allowing efficient hardware implementations. The specification of a hardware block is done by means of LALP, a domain specific language specially designed to help the application of the techniques. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware blocks.

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware description languages (HDLs) such as VHDL or Verilog. The attempts to furnish a high-level compilation flow (e.g., from C programs) still have open issues before efficient and consistent results can be obtained. Bearing in mind the FPGA resources, we have developed LALP, a novel language to program FPGAs. A compilation framework including mapping capabilities supports the language. The main ideas behind LALP is to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to permit the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. In this paper we describe LALP, and show how it can be used to achieve high-performance computing solutions.

Wide-issue ILP machines can be built using the VLIW approach as many of the hardware complexities found in superscalar processors can be transferred to the compiler. However, the scalability of VLIW architectures is still constrained by the size and number of ports of the register file required by a large number of functional units. Organizations composed of clusters of a few functional units and small private register files have been proposed to deal with this problem; an approach highly dependent on scheduling and partitioning strategies. The paper presents DMS, an algorithm that integrates modulo scheduling and code partitioning in a single procedure. Experimental results have shown that the algorithm is effective for configurations up to 8 clusters, or even more when targeting vectorizable loops.