A novel gate-level high-speed VLSI logic simulation technique with assignable delay is presented that uses bitwise logic operations together with the segmented waveform relaxation method (SWRM). The implementation of the technique on parallel computers is described. Although the proposed technique is similar to the compiled-code method, it does not generate a compiled-code and can handle different delay methods which cannot be handled by the conventional compiled-code method. By using waveform relaxation techniques, the simulation can always find the correct logic level in tightly coupled feedback circuits (such as flip-flops), while event-driven simulation may not give the correct logic levels in these cases. The proposed simulator reduces the memory requirements and computation time by using segmented waveform relaxation. On a single processor the simulator is about one order of magnitude faster than the traditional event-driven simulators and can easily handle tens of thousands of gates.>

A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation.>