Modern real-time embedded systems increasingly use runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, reconfiguration delay is non-negligible and varies due to resource contention. Unlike existing solutions that affect system resources or timing, this paper presents an approach and tools to provide a safe, tight reconfiguration delay bound by accurately modeling contention, without additional resource usage, and applicable to most embedded Systems-on-Chip. Additionally, by using Quality-of-Service mechanisms available in modern systems-on-chip, the proposed approach allows designers to set an upper limit for the reconfiguration delay and maintain it against interference from competing tasks. To evaluate the proposed approach, we present two experiments in which it is applied to a representative configuration on a Xilinx Zynq UltraScale+ platform. Experimental results indicate that the reconfiguration delay bound holds under induced worst-case interference scenarios, ensuring that, under heavy workload conditions, the reconfiguration delay can be up to 6.3 times its value in isolation. Moreover, the approach can automatically generate a quality-of-service configuration that ensures a maximum reconfiguration delay 1.8 times its value in isolation, with only a 14% slowdown on contenders and no additional resource consumption, outperforming the existing state of the art. • An approach to emulate worst-case contention for Dynamic-Partial Reconfiguration. • A tool to inject traffic and characterize Dynamic Partial Reconfiguration delay. • QoS-based mitigation ensuring timing isolation for Dynamic Partial Reconfiguration.

As embedded systems are required to satisfy increasing functional and non-functional requirements, heterogeneous systems-on-chip architectures are progressively adopted. While these complex systems-on-chip deliver high performance, they require efficient coordination of the tasks they carry out. To tackle this challenge, designers often resort to runtime mechanisms allowing the dynamic alignment of application requirements with platform services. In turn, runtime mechanisms require the adoption of on-chip monitoring systems. The integration of on-chip monitoring systems into a system-on-chip results in a monitored system-on-chip. Notwithstanding, this integration risks driving a re-design and a re-implementation of the whole system-on-chip, potentially driving to a time-to-market deadline miss. In the literature, HW/SW co-design approaches for monitored systems-on-chip have been proposed to overcome the problem. However, the existing HW/SW co-design approaches prevent performing a system-level design-space exploration that involves all the monitoring requirements, and they also prevent adequate reuse of existing on-chip monitoring systems. This article proposes an approach for efficient HW/SW co-design of monitored systems-on-chip, aiming to comprehensively capture all monitoring requirements at the system-level and to perform a system-level design-space exploration to satisfy them, enforcing the reuse of existing on-chip monitoring systems. The proposed approach is validated through two experimental activities, which demonstrate a 24% reduction in total development time for a monitored system-on-chip implemented on FPGA, compared to the customary approach. The results also show that the approach reduces the risk of missing time-to-market deadlines, supports flexible design choices, and enables the reuse of on-chip monitoring systems.

The Internet of Things is promising as it drives the datafication of our everyday life and thus, leverages synergies between originally considered “dead” things and enables them to proactively serve humans. IoT5.0, an Artificial Intelligence assisted Internet of Things, could even more benefit society, as the devices could even learn how to provide more value. But the ubiquitous connectivity comes at a cost. Security levels have to rise tremendously to ensure a network stays secure and safe for humans. This additional effort often is a burden for small and medium sized enterprises as the complexity and security demands of such systems rise faster than available resources. Consequently., RESILIENT TRUST focuses on end-to-end security of IoT processing chains with a focus on strong exploitation for SMEs. Moreover, RESILIENT TRUST will address and significantly mitigate the major risks to enable IoT 5.0. That way., this project will be a driver for sustainable development and the generation of convenience and wealth. A solution is proposed to ensure end-to-end security by boosting RESILIENCE and TRUST along different key supply chains of IoT device.

Electronic Design Automation (EDA) is a crucial research area related to the development of electronic systems. In particular, High-Level Synthesis (HLS) simplifies HW design by automatically translating C/C++/System C specifications into HW description languages. However, HLS for large systems can be time-consuming. In recent years, Machine Learning (ML) has emerged as a prominent topic in EDA, with numerous studies demonstrating its potential to enhance EDA methods covering nearly all phases of the HW design flow. In such a context, this work presents an approach and related frameworks to collect datasets (i.e., SLIDE-x) useful for performing HLS timing and resource estimation through ML techniques (i.e., SLIDE-x-ML), introducing a data-driven component for feature creation that enhances predictions through various input representations and ML methods.

Abstract Modeling and simulation represent an essential part of overall systems engineering. Complex engineering systems are composed of many heterogeneous components often modeled and simulated employing different languages and environments, and often by different organizations; thus, demands for interoperability are getting increased. Model‐driven engineering (MDE) has been demonstrated to be an advancement in software engineering: existing software in several domains today benefits from abstraction and automation during the system development process. Although these techniques are now highly advanced, many industries may require considerable effort before fully benefiting from them. This article reports on a case study carried out for 12 months within a company in the space industry domain. The goal of this empirical study is to investigate the adoption of MDE in supporting simulation models interoperability. The article identifies factors considered important for MDE adoption as well as obstacles that can be encountered in a real case. Researchers and practitioners may benefit from our findings typically when reusing models across different simulation environments, exchanging simulation models between different stakeholders, and seeking to improve simulation modeling practices.

The objective of the FRACTAL project is to create a novel approach to reliable edge computing. The FRACTAL computing node will be the building block of scalable Internet of Things (from Low Computing to High Computing Edge Nodes). The node will also have the capability of learning how to improve its performance against the uncertainty of the environment. In such a context, this paper presents in detail one of the key use cases: an Internet-of-Things solution, represented by intelligent totems for advertisement and wayfinding services, within advanced ICT-based shopping malls conceived as a sentient space. The paper outlines the reference scenario and provides an overview of the architecture and the functionality of the demonstrator, as well as a roadmap for its development and evaluation.

Nowadays, complex Cyber-Physical Systems (CPSs) often exploit the so-called computing at the edge (i.e., edge-computing), where the Dynamic Partial Reconfiguration (DPR, also known as Dynamic Function eXchange or Partial Reconfiguration) feature has been proved to be efficient to face the adaptivity challenges typical of the CPSs domain. In this context, the increase of both platforms heterogeneity and required customizations are leading to a growth of the number of per-task requested DPR, for which Industry is enhancing the reconfiguration controllers providing the capability to offload more than one DPR request, in turn allowing pipelining between multiple DPR processes and application execution. Several works in literature have introduced the DPR process in the hard real-time system domain, however not considering the multiple DPR offloading capabilities. In this paper, we provide a theoretical analysis and a practical evaluation of multiple DPR offloading in the context of hard real-time systems. In particular, through a motivational case-study, supported by some experimental activities conducted on the Zynq-7000 SoC, we show how the offload of multiple DPR can provide benefits with respect to the traditional approach of one DPR request per time.

Building on many discoveries and inventions, electronics started affecting people’s everyday lives in a significant fashion following the invention of the first solid state transistor in late 1940s. The miniaturization paved way for the mass electronics production and later the digital revolution, the outcomes of which are visible to all members of the public today. After about a two-decade-long swing around 2000s from hardware towards software regarding what affects lives more, a point has now been reached where electronics is more important to all and its use is more ubiquitous and crucial than ever before. In most if not all of end user or industrial applications, the capability and quality of electronics hardware are the key determining factors.The European electronics components and systems (ECS) industry has traditionally had a high base line for electronics innovation. However, the industry is now compelled, partly due to competition and partly due customer demand, to manufacture even more reliable electronics products than before. Guaranteeing the reliability of electronics hardware entails the entire ECS value chain to undergo a paradigm shift to holistically address reliability as a key issue. The European ECS industry previously adopted overseas outsourcing considerably, however it is now taking steps to reshape itself into a more coherent value chain with the aim of having not only the electronics designs but also the electronics manufacturing made in Europe.H2020-ECSEL programme successfully funds highly competitive projects in the area of electronics components and systems. We present here a prologue to a similarly funded project entitled Intelligent Reliability 4.0 ("iRel40"), by providing a background to the topic of ECS, project objectives, and the methodologies and implementations we plan to undertake during the 36-month period of this ongoing project.

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

Raman spectroscopy is a well-established technique for rapid analysis for Cultural Heritage characterization. It represents one of the most used and reliable technique because non invasive and usable, even on-site, without any sample preparation. Overall in the last decade, several methods have been tested with the purpose of obtaining an automatic classification process of spectra of unknown materials. Machine learning methods and in particular Neural Networks are the most recently exploited on this topic. Unfortunately, the availability of real Raman spectra is often limited considering the amount of data necessary for the use of these approaches. In this work we propose a pipeline for augmenting data with a GAN reinforcement, with the aim of creating a dataset large enough to take advantage of such. Furthermore, three types of neural networks (binary-NN, categorical-NN and CNN) are trained with the aforementioned dataset and compared with each other, taking into consideration their accuracy. The results show that the enhanced data augmentation with GANs significantly increases the accuracy of the networks.

Manufacturers of automated systems and their components have been allocating an enormous amount of time and effort in R&D activities. This effort translates into an overhead on the V&V (verification and validation) process making it time-consuming and costly. In this paper, we present an ECSEL JU project (VALU3S) that aims to evaluate the state-of-the-art V&V methods and tools, and design a multi-domain framework to create a clear structure around the components and elements needed to conduct the V&V process. The main expected benefit of the framework is to reduce time and cost needed to verify and validate automated systems with respect to safety, cyber-security, and privacy requirements. This is done through identification and classification of evaluation methods, tools, environments and concepts for V&V of automated systems with respect to the mentioned requirements. To this end, VALU3S brings together a consortium with partners from 10 different countries, amounting to a mix of 25 industrial partners, 6 leading research institutes, and 10 universities to reach the project goal.

The objective of the FRACTAL project is to create a new approach to reliable edge computing. The computing node will be the building block of scalable Internet of Things (from Low Computing to High Computing Edge Nodes). The cognitive skill will be given by an internal and external architecture that allows forecasting its internal performance and the state of the surrounding world. The node will have the capability of learning how to improve its performance against the uncertainty of the environment. New industrial functions will flourish through the created space of the cognitive system. Cognitive advantages are brought to a resilient edge and a computing paradigm that lay down between the physical world and the cloud.

The purpose of this paper is to introduce run time monitoring infrastructures and to analyze trace data inside a well-established component-based methodology. The goal is to show the concept among different monitoring requirements by defining a general reference architecture that can be adapted to different scenarios. Starting from design artifacts, generated by a system engineering modeling tool, and source code automatically generated from UML models, a custom Hardware monitoring sub-system infrastructure will be presented. This sub-system will be able to generate run-time artifacts for run-time verification. We will show how the framework provides round-trip support in the development chain, injecting monitoring requirements from design models down to code and its execution on the platform and trace data back to the models, where the expected behavior will then be compared with the actual behavior. This approach will be used towards optimizing design models for specific properties (e.g, for system performance), using a specific constraint approach compliant with UML standards. Industrial and custom use cases will be used to demonstrate the effectiveness of this approach in real scenarios.

This paper deals with the design and implementation of security mechanisms in Wireless Sensor Networks(WSN) based applications, without the support of external “resource unconstrained” facilities. In particular, this paper provides a global overview of a long lasting research project and then reports on recent design upgrades denoted as the “Secure Platform”. This has been the target of the SEAMLESS Project, that was oriented to design and validate monitoring architectures for Internet of Things services such as services ranging from featuring temperature, humidity, pressure, light, accelerometer, GPS to non-conventional operational scenarios for military surveillance. This paper then reports security and performance test results of the main components in the “Secure Platform”: the Topology Authenticated Key Scheme (TAKS) and the WPM-based Intrusion Detection System (WIDS). The measurement campaign involved the typical parameters (e.g., encryption / decryption time, key generation time) and a conventional statistical analysis on the results has been also performed.

Cyber-Physical Systems (CPS) are dynamic and reactive systems interacting with processes, environment and, sometimes, humans. They are often distributed with sensors and actuators, smart, adaptive, predictive and react in real-time. Indeed, as sight for human beings, image- and video-processing pipelines are a prime source for environmental information for systems allowing them to take better decisions according to what they see. Therefore, in FitOptiVis we are developing novel methods and tools to integrate complex image and video processing pipelines. FitOptiVis aims to deliver a reference architecture for describing and optimizing quality and resource management for imaging and video pipelines in CPS both at design- and run-time. The architecture is concretized in low-power, high-performance, smart components, and in methods and tools for combined design-time and run-time multi-objective optimization and adaptation within system and environment constraints.

Wireless Sensor Networks (WSNs) are nowadays used in a variety of applications, to monitor relevant quantities often in large and harsh environments, thanks to their flexibility and versatility. Unfortunately, the nature of the wireless communication channel exposes WSN nodes to security risks. Conventional security countermeasures cannot be applied to the WSN nodes due their resource limitations. In this paper, we propose a lightweight blockchain approach to contrast the physical or logical tampering of WSN nodes. We validate our approach through experiments showing the performance impact and the storage footprint due to the use of the proposed blockchain anti-tampering technique. The proposed approach appears to be suitable in the context of WSNs, although the overhead generated by the blockchain depends on the number of nodes in the WSN.

The presented Ph.D. project deals with the definition of an Electronic System-Level methodology, and the development of related prototype tools, for the exploitation of FPGA with the Dynamic Partial Reconfiguration feature. The goal of the project is to provide a Design for the ReConfigurability approach able to identify, at design-time, a set of system configurations that allow satisfying functional and non-functional requirements. Such configurations are then exploited, at run-time, by a system manager that is also able to take into account the reconfiguration cost to fully evaluate pro and cons of such a process. While the proposed Ph.D. project is still under development, its current status is described highlighting the planned works.

Cyber-Physical Systems (CPS) are systems that are in feedback with their environment, possibly with humans in the loop. They are often distributed with sensors and actuators, smart, adaptive and predictive and react in real-time. Image- and video-processing pipelines are a prime source for environmental information improving the possibilities of active, relevant feedback. In such a context, FitOptiVis aims to provide end-to-end multi-objective optimization for imaging and video pipelines of CPS, with emphasis on energy and performance, leveraging on a reference architecture, supported by low-power, high-performance, smart devices, and by methods and tools for combined design-time and run-time multi-objective optimization within system and environment constraints.

Farming is facing many economic challenges in terms of productivity and cost-effectiveness. Labor shortage partly due to depopulation of rural areas, especially in Europe, is another challenge. Domain specific problems such as accurate identification and proper quantification of pathogens affecting plant and animal health are key factors for minimizing economical risks, and not risking human health. The ECSEL AFarCloud (Aggregate FARming in the CLOUD) project will provide a distributed platform for autonomous farming that will allow the integration and cooperation of agriculture Cyber Physical Systems in real-time in order to increase efficiency, productivity, animal health, food quality and reduce farm labour costs. This platform will be integrated with farm management software and will support monitoring and decision-making solutions based on big data and real-time data mining techniques.

This paper presents an overview of the project CASPER, a Marie Curie Research and Innovation Staff Exchange (RISE) project running from 2016 until 2020. The main objective of CASPER is to combine academic and industrial forces towards leveraging the expected benefits of Quality of Experience (QoE) exploitation in future digital networks. In particular, CASPER exploits the most recent advances in communication networks, such as the Software Defined Networking (SDN) and the Network Functions Virtualisation (NFV) in order to design and implement a middleware architecture for QoE-driven service provisioning. CASPER, therefore, addresses the challenges that mobile network operators and service providers face in the current fully digitalized era of communications, concerning the need to provide customer-oriented, reliable, efficient, flexible and dynamic service management.

Heterogeneous parallel devices are becoming widely diffused in the embedded systems application field since they allow to improve time performances and other orthogonal metrics (e.g., cost, power, size, etc.) at the same time. In such a context, the introduction of safety requirements, as dictated by the relevant standards (i.e., DO-178 B/C and RTCA/DO-254 in airborne systems, ARINC 653 for avionics software, ISO-26262 in automotive domain, etc.) while considering shared resources on a heterogeneous parallel HW platform, adds further challenges to industrial and academic research. This kind of platforms that execute tasks with different levels of criticality are commonly called mixed-criticality embedded systems. So, the main problem in their management is to ensure that low criticality tasks do not interfere with high criticality ones. The final goal is to allow several applications to interact and coexist on the same platform. For this, the exploitation of virtualization technologies (i.e., hypervisors) allows to guarantee isolation and to satisfy certification requirements but introduces scheduling overhead and new HW/SW partitioning challenges. In such a scenario, this work focuses on a framework for modeling, analysis, and validation of mixed-criticality and real-time systems based on an existing "Model-Based Electronic System Level HW/SW Co-Design" methodology. The main contribution of this work is the integration of the considered framework with Xamber tool in order to provide systems implementations by exploiting a design space exploration able to consider Xtratum-based SW partitions.

This work faces the role of Design Space Exploration for embedded systems based on heterogeneous parallel architectures and subject to mixed-criticality system requirements, while considering the exploitation of hypervisor-based SW partitions to better manage isolation. In particular, it presents an evolutionary partitioning and mapping approach integrated into a reference Electronic System Level HW/SW Co-Design framework to propose and early validate design solutions by means of HW/SW Co-Simulations.

There is an ever-increasing complexity of the systems we engineer in modern society, which includes facing the convergence of the embedded world and the open world. This complexity creates increasing difficulty with providing assurance for factors including safety, security and performance. In such a context, the AQUAS project investigates the challenges arising from the inter-dependence of safety, security and performance of systems and aims at efficient solutions for the entire product life-cycle. The project builds on knowledge of partners gained in current or former EU projects and will demonstrate the newly developed methods and techniques for co-engineering across use cases spanning Space, Medicine, Transport and Industrial Control.

Landslides constitute one of the most important natural hazards in many countries all over the world. Due to such fatalities, a lot of attention is dedicated to the safety assessment and monitoring of assets of public relevance for either local or state administrations. Railway stations and lines represent a relevant category of elements because of their intrinsic economic value and because their damage may cause human casualties as well. However, if attempts to assess the safety of assets consider large geographic areas, the number of assets potentially exposed at risk would be very high. So, the opportunities to exploit real-time monitoring technologies, e.g. Wireless Sensor Networks (WSN), would be too much costly. To mitigate such issues, this paper presents an innovative framework for a cost-effective monitoring of landslides applied to railway stations and lines that combines the use of WSN technologies with an existing Geographical Information Service (GIS) based ranking method. A case study focused on the Abruzzo Region of Italy shows the potential benefits of such an integrated approach.

The CASPER project envisions the user-centric network and service management in future mobile networks. In this frame, this paper aims at studying the impact of packet loss rate (PLR) and end-to-end delay (E2E delay) induced by quality of experience (QoE)-aware management policies in real LTE networking conditions with Voice over IP and video streaming traffic patterns. This objective is achieved by implementing a simulation framework built upon SimuLTE/OMNeT++ to reproduce the CASPER reference scenarios. The results demonstrate that there is a clear trade-off between the PLR and E2E delay that needs to be taken into account to keep acceptable OoE levels.

A major challenge for the European electronic industry is to enhance productivity while reducing costs and ensuring quality in development, integration and maintenance. Model-Driven Engineering (MDE) principles and techniques have already shown promising capabilities but still need to scale to support real-world scenarios implied by the full deployment and use of complex electronic components and systems. Moreover, maintaining efficient traceability, integration and communication between two fundamental system life-time phases (design time and runtime) is another challenge facing scalability of MDE. This paper presents an overview of the ECSEL project entitled "MegaModelling at runtime -- Scalable model-based framework for continuous development and runtime validation of complex systems" (MegaM@Rt2), whose aim is to address the above mentioned challenges facing MDE. Driven by both large and small industrial enterprises, with the support of research partners and technology providers, MegaM@Rt2 aims to deliver a framework of tools and methods for: 1) system engineering/design & continuous development, 2) related runtime analysis and 3) global model & traceability management, respectively. The diverse industrial use cases (covering domains such as aeronautics, railway, construction and telecommunications) will integrate and apply such a framework that shall demonstrate the validation of the MegaM@Rt2 solution.

Nowadays embedded systems are powerful and everywhere. They implement complex functionality relying on a huge set of different hardware and software (HW/SW) architectures. In order to reduce their development effort, HW/SW Co-Design techniques are used during the entire development cycle. These techniques aim at helping designers to define a feasible hardware and software partitioning for the system in such a way that functional and non-functional requirements are fulfilled. In this context Design Space Exploration is a challenging activity since a huge number of different implementation alternatives need to be evaluated.

The Safe Cooperating Cyber-Physical Systems using Wireless Communication (SafeCop) project addresses safety-related issues in cooperating cyber-physical systems. These systems, characterised by wireless communications, multiple stakeholders, and variable operating environments, are called Cooperative Open Cyber-Physical Systems (CO-CPS). CO-CPSs can successfully address several societal challenges -- cooperative vehicles have been shown to reduce fuel consumption as well as the number of accidents. A vehicle-to-infrastructure (V2I) cooperation for the traffic management scenario is therefore considered as a key use cases of SafeCop. In this paper, we outline the V2I traffic management scenario, assess the research goals that arise from it, and provide an overview of the architecture of the demonstrator, as well as a roadmap for its development and evaluation.

In recent years, embedded applications have been characterized by increasingly stringent requirements, both from functional and non-functional point of view. This led to the adoption of complex hardware platforms (multi-core and many-core architectures), able to guarantee high computational power with low energy consumption and reduced footprint. An efficient characterization of these platforms can be problematic, given the large number of hardware resources and the complexity of software applications. For this reason, the need for a runtime analysis support should be taken in account during the design phase (a design "for monitorability"). This paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems. Two different multicore platforms are considered in order to evaluate AIPHS functionalities: an asymmetric dual-MicroBlaze system and a quad-Leon3 system supporting symmetric multiprocessing.

This paper deals with the design and implementation of security mechanisms in networked embedded systems (e.g. Wireless Sensor Networks (WSN)), without the support of external “resource unconstrained” facilities. While most literature contributions propose to put intelligence (that is usually more consuming both in computational resources and in memory as well) outside the WSN, we have already reported in some previous works that, under certain limitations, a WSN can operate as a functionally “autonomous entity” not only for sensing operations. This paper provides a global overview of the related research project and then reports on recent design upgrades to what we denote as the “Secure Platform”, i.e. the SW platform over WSN that is able to support a wide range of applications in non-standard environment such as monitoring of critical infrastructures, data acquisition in hazardous environments under standard security conditions. The work presented here is a partial achievement of the internal project WINSOME (WIreless sensor Network-based Secure system fOr structural integrity Monitoring and AlErting) at our Centre DEWS, whose target is to develop a cross-layer secure framework for advanced monitoring and alerting applications.

This work faces the problem of the HW/SW co-design of dedicated systems based on heterogeneous multi-processor architectures. In particular, it proposes a system-level design space exploration approach that allows the related co-design methodology to suggest an HW/SW partitioning of the application specification and a mapping of the partitioned entities onto an automatically selected heterogeneous multi-processor architecture. The modeling strategy and the description of the adopted heuristic and metrics represent the core of the paper while a simple case study allows clarifying the main features of the whole approach.

This paper presents a project that has been recently funded by means of the ERC Starting Grant (http://erc.europa.eu/). The main goal of the project is to develop a new generarion of wireless sensor networks infrastructure to support innovative services for ubiquitous sensing and video. The work is in a very preliminary phase so the paper presents a general overview and the main challenges.

Understanding the real behavior of a Wireless Sensor Network application before the implementation enables engineers to reduce development time and cost because it makes possible the optimization of system resource utilization. In this context, this paper present an extension to an existing reference framework in which the designer can build network components, consider details about physical layer and communication medium, easily exchange the WSN configuration, simulate it by analyzing several parameters and finally generate code for different target hw/sw platforms.

The demonstration proposal moves from the capabilities of a wireless biometric badge [4], which integrates a localization and tracking service along with an automatic personal identification mechanism, to show how a full system architecture is devised to enable the control of physical accesses to restricted areas. The system leverages on the availability of a novel IEEE 802.15.4/Zigbee Cluster Tree network model, on enhanced security levels and on the respect of all the users' privacy issues.

The demo we propose represents a first step toward RF Sounding [1]. Such a project is an open space installation which comprises both artistic and technological innovations; its aim is to provide the user, while entering a specifically defined area, with awareness of radio frequency signals characterizing the cellular networks band. Indeed, radio signals are shifted, with proper elaboration, to the audible band and the result is spread all over the specific area through a certain number of loudspeakers. For this procedure we have been inspired by the eternal metaphor of the impossible human dream to fly, thus the limitations of our senses which are capable of feeling audio waves (sounds) but (maybe luckily) are not capable of directly feeling radio frequency (RF) waves are highlighted. The translation is the starting point for a more complex and exciting musical composition. It has to be underlined that some features of RF sensed signals are kept unchanged in order to give to the listener the clear feeling of the amount (power) of RF signals present in the monitored area. The aim of this project is twofold. Indeed, from one side we want to increase end users knowledge of the strength of the power emitted by their cellular phones with respect to the electromagnetic fields produced in the environment, on the other hand we want to provide for an artistic and interactive installation that can also be remotely joined through a web interface.

The demonstration proposal focuses on presenting the capabilities of a wireless biometric badge, which integrates a localization and tracking service along with an automatic personal identification mechanism, to control the access to restricted areas with a high level of security. The wireless biometric badge is the result of R&D activities conducted by several professors, researchers, and students in the Center of Excellence in Research DEWS at the University of L' Aquila in Italy, as well as its R&D Spin-Off WEST Aquila S.r.l.

This paper focuses on the analysis of fundamental issues which has to be considered in order to gain voice from a wireless sensor network (WSN) that is assumed to be constituted by MicaZ wireless sensor nodes. Problems related to the transport of an audio signal through a wireless channel and sensor nodes are thus analyzed and a project for an audio surveillance system is presented.

The ability to run spatial queries is extremely useful for wireless sensor networks. Spatial query execution has been extensively studied in the context of centralized spatial databases; however because of the energy and bandwidth limitation of sensor nodes these solutions are critical to wireless sensor networks. In this paper, we propose an extension of TinyDB suitable to manage the location of sensor nodes and, hence, able to process besides standard queries, spatial queries as well. The proposal has been implemented and validated.

Continuous advances in silicon technology enable the development of complex system-on-chip as cooperation among digital signal processors (DPSs), general purpose processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC) - statically and in a fast manner - and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected hardware-software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper.

The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments. Such design methodologies tackled the problem at different abstraction levels, from switch-level to logic, RT level, and more recently to system level. The aim of this paper is to introduce a novel system-level technique based on the redefinition of the operator functionality in the system specification. This technique provides reliability properties to the system data path, transparently with respect to the designer. Feasibility, fault coverage, performance degradation and overheads are investigated on a FIR circuit.