Automatic test equipment (ATE) for highperformance memory devices needs to transmit and receive ultra-high-speed data/clock waveforms with high fidelity. So far, this has been achieved by applying intricate calibrations with external equipment, which requires significant time, cost, and effort. This paper proposes a method for estimating S-parameters of signal paths to DUT using time-domain reflectometry (TDR), which enables automated calibration for a large number of ATE pins by utilizing built-in drivers and comparators. The proposed method compensates for the effects of reflections from the signal path and the characteristics of the comparator circuit, which affect the TDR measurement results, and enables the accurate prediction of the waveform at the calibration point. Furthermore, without the necessity for external equipment, the proposed method realizes the calibration of a massive number of pins in a short time at a low cost.

This paper proposes a new method of constructing a compensation filter for the modulated wideband converter (MWC) system. The proposed method can be directly used in the MWC circuit without disconnecting any components. Furthermore, the non-ideal transfer characteristics of the real mixer output and the real ADC input are taken into account in the proposed compensation filter. The proposed method can be utilized in the advanced MWC that enables more flexibility in the design parameters of the MWC. This paper also demonstrates the reconstruction of the Bluetooth signal as a practical example for the evaluation of the reconstruction performance. The MWC successfully reconstructs the time-domain waveform of the signal based on the proposed compensation filter. Even in the case that the total effective number of channels in MWC is small as close to the necessary condition of the MWC, the error vector magnitude (EVM) was still under 1%, which is acceptable for Bluetooth device testing applications.

This paper describes the application of our previously proposed residue sampling circuit to RF/Analog Mixed-Signal (AMS) device testing. The residue sampling circuit provides high-frequency signal estimation using multiple low-frequency sampling circuits following an analog Hilbert filter and ADCs; the sampling frequencies are relatively prime. It is based on aliasing phenomena in the frequency domain for waveform sampling and the residue number theory. A high frequency cosine wave is provided as an input signal. Cosine and sine signals with the same frequency are generated by an analog Hilbert filter and are fed into sampling circuits with different (relatively prime) low sampling frequencies. Their analog outputs are analog-to-digital converted and complex FFT is performed on both. Since the high frequency signal is sampled with low frequency clocks, aliasing (spectrum folding) occurs. However, each aliased frequency is different because each sampling clock frequency is different in the sampling circuits. Based on the Chinese remainder theorem, this difference allows the input frequency to be estimated. High frequency resolution can be achieved over long time periods and large numbers of FFT points. We consider here applications to RF/AMS device testing; (i) two tone testing for high frequency narrow band devices, (ii) wireless communication device testing such as LTE, Bluetooth and (iii) wideband analog filter frequency characteristics testing. These considerations are supported by simulations.

The Modulated Wideband Converter (MWC) is one of the promising sub-Nyquist sampling architectures for sparse wideband signal sensing, cognitive radio applications and so on. In order to design an MWC-based RF receiver that meets a target RF specification, noise figure (NF) of the MWC has to be well-defined by its design properties. This paper reviews a comprehensive explanation for NF of MWC by an analytic approach based on a notation of an average noise figure (ANF) of the MWC, which has been detailed in our prior work in [1]. Consequently, the analysis is proven with simulation and measurement results in order to demonstrate its feasibility.

This paper describes the similarity of the crest factor reduction effect among the four algorithms (Newman, Kitayoshi, Schroeder and Narahashi) and unifies their initial phase setting equations using the derivation of the Narahashi phase. When testing the frequency characteristics of analog/mixed-signal ICs, a multi-tone (sum of multiple sine waves) signal is often used instead of a single tone signal, to reduce their testing time. However, as the amplitude of each tone signal becomes smaller if multiple sine waves are simply added without care of their initial phases, the SNR of the test result becomes worse and the test accuracy becomes lower. To alleviate this problem, it is necessary to generate a multi-tone signal using a crest factor reduction algorithm. There are four representative multi-tone signal generation algorithms for reducing crest factor, and their study results are presented.

Recently, bandwidth for wireless communications are getting wider, i.e. 400 MHz for the 5th generation mobile communication (5G), and about 2 GHz for wireless LAN (IEEE 802.11ad). To evaluate the transceiver devices used in these communications, a high-speed waveform digitizer is required. In this paper, the Sweep Digitizing Method which accurately captures ultra-wideband signals covering 2 GHz with low cost is introduced. It is a method of decomposing a wideband signal transmitted at a high frequency into subband signals of several hundred megahertz bandwidths while downconverting it to an intermediate frequency, and capturing it for each subband signal by a low speed waveform digitizer. The captured waveform is synthesized by post digital processing. At this time, a correction process for matching the carrier phase and the conversion gain of each subband signal is performed. In this method, an ultra-wideband signal can be captured by a single low-speed high-resolution analog-to-digital converter (ADC) and the measurable bandwidth can be easily controlled by adjusting the Local Sweep section.

This paper investigates multi-tone signals for short-time and high quality testing of analog circuit frequency response. First, we study three multi-tone signal generation algorithms for minimum crest factor using an arbitrary waveform generator, and show that they are comparable. Then we propose crest factor controlled multi-tone signal generation algorithms for effective testing of transmitters. These algorithms are verified with simulations.

This paper describes algorithms, simulation and experiment verifications of a novel harmonic distortion suppression technique for an arbitrary waveform generator (AWG). It can automatically suppress the harmonics and the image components over a full Nyquist region of the AWG by preprocessing the sinusoidal waveform data using "phase switching method". We show this technique can apply to cancel the harmonics from mid-frequency regions. Also we show two-tone signal generation with IMD suppression. With these methods, distortion components close to the signal are suppressed simply by changing DSP program or waveform memory contents-AWG nonlinearity identification is not required-and spurious components, generated far from the signal band, are relatively easy to remove using an analog filter.

The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.

This paper proposes low-distortion sinusoidal/two-tone signal generation techniques for analog/mixed-signal IC testing with a digital Automatic Test Equipment (ATE) using only single digital output pin. They provide a rectangular waveform approximated to a single-tone or two-tone with specified harmonics suppression; we can specify multiple harmonics to suppress using digital control, and it is followed by an analog LPF for smoothing. The proposed method is simple for implementation with modest performance, compared to a wide dynamic range delta-sigma DAC. Its configuration, principle, simulation as well as experimental results at the laboratory level are presented. Also its application, combined with a high-speed DAC for analog circuit testing is described.

This paper proposes signal generator (BIST/BOST) algorithms and architectures for mixed-signal IC testing input. They can provide rectangular waveforms approximated to single-tone and/or two-tone signals with harmonics/IMD suppression. Their circuit consists of digital circuit, a 1-bit DA converter with an analog filter. Proposed method is simple for implementation with modest performance, compared to a wide dynamic range delta-sigma DAC [1, 2] and other methods [3-5].

Today, as LSI devices are increasingly more integrated resulting in larger number of package pins, high speed signal lines are more easily coupled to each other. Additionally, since multisite testing is required to reduce the cost of test, the transmission lines connecting these pins become even more concentrated. To measure these LSI devices, a huge number of high-speed transmission lines are required in the test board. Therefore minimizing crosstalk is very important. Furthermore, since the number of channels have reached more than ten thousand in recent evaluation systems, it is strongly required that the crosstalk from all channels be measured. With so many channels, measuring crosstalk with traditional methods will at best be very time-consuming or at worse, completely impractical, as it requires either a large number of pulse generators or physical reconnections depending on measurement type. In this paper, we propose a very fast and low cost crosstalk measurement method, which can acquire results very quickly and with high frequency resolution. Only a single measurement makes it possible to evaluate the crosstalk over a wide frequency band without the repetition of manually measuring at each frequency. This method is highly beneficial to the automatic test equipment (ATE) environment with high density transmission lines on the performance boards or load boards.

This paper describes a digital method of reducing timing mismatch effects in time-interleaved ADCs used in ATE systems: we use cross-correlation among channel ADC outputs to detect channel timing skew, and make successive-approximation adjustments to our proposed linear-phase-digital delay filter to compensate for the timing skew. Simulation results validate the effectiveness of the proposed method. We found that using multitone input signals with cross-correlation of outputs provided a more robust way of detecting timing skew than using a singletone input signal. Since our proposed approach is fully digital, it is reliable, and suitable for fine CMOS implementation.

Since recent wireless communication devices support multiple communication standards on a single chip, Error Vector Magnitudes (EVMs) for multiple standards are measured to evaluate the devices. The EVM is defined by the particular calculation methods of the communication standards, especially channel correction methods. Therefore the EVM value is different between standards, even if the modulation methods are identical. This paper describes an EVM evaluation method for multi-standard devices, performing channel correction particular to each standard. The EVM for the various standards can be calculated by a unique algorithm, which uses the values of the frequency-dependent I/Q imbalances and the Signal-to-Noise Ratio (SNR) calculated from a single measurement data. The validity of this technique is confirmed using an actual WiMAX transceiver on an ATE.

As bandwidths of digital wireless communications get wider, it is essential to evaluate the I/Q imbalances among quadrature mixer ports in terms of the mismatch characteristics of the analog components in the I and Q paths and the carrier phase offset. This paper describes a technique to evaluate frequency-dependent I/Q imbalances and carrier phase offset in wideband quadrature mixers. Using an SSB stimulus, the response of a DUT with imbalances is modeled mathematically, and an identification algorithm using a unique input stimulus is constructed. The validity of this technique is confirmed using an actual WiMAX transceiver on an ATE.

This paper describes the timing skew compensation technique using the digital filter with our novel linear phase condition. First we describe the digital filter which can set its group delay with the arbitrary fine time resolution while it maintains the linear phase characteristics; the conventional linear phase digital filter can set its group delay with the time resolution of a half of the sampling period. We will provide its structure and operation, theoretical analysis as well as simulation verification. Next we will describe the application of our proposed digital filter to compensate for timing skew in the following cases: (1) Sampling timing skew among channels in the time-interleaved ADC system. (2) I, Q-path timing skew in the single-side band (SSB) signal generator. We show its effectiveness with simulation.

Interleaving is one method of configuring a highspeed waveform digitizer. Degradation of the dynamic range, however, results from co-channel mismatched characteristics among the individual ADCs. Especially, mismatches of the non-linear characteristics have not been analyzed so far. This paper constructs a mathematical model, and proposes a method for correcting mismatches of both linear and non-linear characteristics using a digital signal processing technique. This method does not require any additional hardware.

As wide-band wireless communications become increasingly prevalent, evaluation of balance among quadrature mixer ports, in terms of carrier phase offset, gain mismatch, and IQ skew, becomes essential. Due to the difficulty of separating skew, gain imbalance and carrier phase offset, evaluation, such as by taking measurements while calibrating, is time consuming. For this reason, test is often performed using a composite value, without separation of error factors. This paper describes an algorithm for performing accurate measurements while enabling separation among quadrature mixer gain imbalance, carrier phase offset, and skew. Thanks to the short test time of the proposed method, it can be applied during high volume production testing.

Interleaving is one method of configuring a high-speed waveform digitizer. It is known that, in this method, using multiple A-D converters (ADC) enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead

WCDMA test applications using an arbitrary waveform generator (AWG) are described in this paper. A test signal generation method for the receiver section of a WCDMA handset is described with a center frequency of 161.28 MHz containing a 5 MHz spread spectrum signal. The arbitrary waveform consumes 2.6 M AWG memory locations running at 3.9 Gs/s. The 1.5 kHz primitive frequency is sufficient for generating WCDMA test chips described by the 3/sup rd/ generation partnership project (3GPP) by using modulation techniques. Other data processing for creation of the test signal include the application of a channelization code to provide orthogonal data, a scrambling code, and a root Nyquist filter for reducing the frequency content around the 161.28 MHz center. An enhancement for bit error rate tests using controllable Gaussian noise for testing receiver tolerance and acceleration of bit error rate measurements is also discussed.

One method for achieving high-speed waveform digitizing uses time-interleaved Analog-to-Digital Converters (ADC's). Time interleaving with two or more ADC's enables waveform digitizing at sampling rates proportionately faster than when using just one ADC. A well-known drawback of this method is that the misalignment of sampling instances degrades the achievable dynamic range. This paper proposes a solution that removes distortion caused by the alignment error with digital signal processing. Since the algorithm is realized as an extension to the ordinary FFT, the objective is achieved without significant loss of throughput.

Intermediate frequency (IF) signal output devices, with the quadrature mixer integrated into the modulation unit of the base-band LSI, are used with the Personal Handyphone Systems (PHS). It's known that modulation accuracy is a parameter for synthetic evaluation of the accuracy of IF modulation signals. This paper discusses an algorithm for fast measurement of this parameter. The results of this algorithm were evaluated using a mixed signal IC test system.