This article presents analytical tools for high-level design of the leapfrog (LF) control-bounded analog-to-digital converter (CBADC). We derive closed-form design equations for parameterizing the analog system for a target signal-to-noise ratio (SNR) and bandwidth. Furthermore, we show how the parameterization can be modified to compensate for finite amplifier gain-bandwidth product (GBWP) and to control the signal swing at different nodes of the system. Behavioral circuit simulations are used to compare the LF CBADC to relevant continuous-time sigma–delta modulators (CT-$\Sigma \Delta $Ms) in terms of nominal performance and sensitivity to component variations, clock jitter, and finite GBWP. Simulations show that the nominal performance of the LF is similar to that of a CT-$\Sigma \Delta \text{M}$of the same loop-filter order and with the same number of quantization levels. The simple, modular structure, analytical stability guarantee, and single-bit quantizers make the LF an interesting alternative to conventional CT-$\Sigma \Delta $Ms.

This paper presents a differential Power Amplifier (PA) for operation in the D-band. The simulated PA has gain of 8 dB/stage at 160 GHz for a total gain of 32 dB, a saturated output power of 11 dBm, a peak power added efficiency (PAE) of 9.8%, and a 3-dB bandwidth of 7 GHz. The PA consumes a power of 112 mW from 1.1 V supply. The PA core area is 0.052 mm 2 in 28-nm FD-SOI technology.

Low power data management is an approach that distribute the supply power on the various modules in the chip, following certain algorithms such as dynamic voltage sharing (DVS), single input multiple data (SIMD) among others with a coil-less circuit design. The key factors for reducing the power and enhancing the efficiency is attributed to the lower feeding power supply, high device mobility for low power consumption, the device size, and the architecture used in the design. Graphene Nano Ribbon Field Effect Transistors (GNRFET) based Buck and Boost converters were designed for single input/multiple outputs conversion. The design features very high efficiency that exceeds 90% at very high frequencies. The input was 0.7V with outputs of 0.35V and 1.4V for buck and boost converters respectively. The design gains from the high mobility feature of the nano scale GNRFET devices, and the low supply power applied to the various modules in the chip. A 10nm scale channel device with 4 ribbons were considered, and the switch capacitor (SC) approach was utilized. The study of the transient analysis, the static power, dynamic power, and ripple voltages at different design constraints were investigated versus the conversion parameters including the frequency, load, and duty cycles. The efficiency at a high load was estimated to be near 97%, while at low load and lower switching frequencies, the efficiency was estimated to be near 85%.

A novel approach to merge superconducting Josephson Junction (JJ) devices with nanoscale Graphene devices in order to achieve high gain-bandwidth-product on the order of THz was addressed. JJs are ultra-fast devices that consist of two superconducting plates separated by a nanoscale layer of nonconducting material which exhibits quantum tunneling phenomenon. While JJ-based devices have existed since nearly 1962, interfacing them with standard electrical systems has been a challenge for several reasons, including operating temperature, switching speed, and low-signal sensitivity. In this study, we investigated the possibility of utilizing JJ's so-called AC-effect in order to generate high frequency signals that can be accommodated by high speed nanoscale devices. Graphene Nano Ribbon Field Effect Transistors (GNRFET) have been emphasized for their very high frequency operation that is appropriate to accommodate the very high switching speed of the JJ devices. The study is based on the AC JJ effet with generating a sinusoidal current whose frequency directly scales with voltage. For a single-stage GNRFET CS amplifier, a gain of 35.7dB with a bandwidth of 217GHz was achieved, while 10.8dB with a unitary gain of 2.5THz was also accomplished. The paper details the design and interfacing of the JJ with GNRFET devices, targeting high frequency signal generation on the order of hundreds of GHz to THz.

This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.

This paper presents a high-voltage three-level pulse-generator circuit which reduces the driving requirement of the input signals. This is achieved by cascoding making it possible to use low-voltage input transistors. The reduced driving requirement of the input signals makes it possible to use simple two-component capacitive level-shifters. The circuit is implemented in a commercially available 180nm high-voltage CMOS process. Circuit functionality is verified by simulation on schematic and layout using high supply voltages of positive and negative 70V. Simulation results indicate a reduction in input gate-charge by a factor of about 28. Average power consumption of about 0.61mW and 0.44mW is observed for a three-level and a two level 4-period 5MHz pulse using a pulse-repetition frequency of 5kHz.

Oversampling and noise-shaping have in recent years been introduced to SAR ADCs to improve the conversion accuracy. Similar to delta-sigma ADCs, this is done by means of a feedback loop containing a loop filter. In this paper, the high-level design of this loop filter is discussed, and important differences to classical delta-sigma loop filter design are pointed out. Among others, it is found that the poles of the noise transfer function, and not only the zeros, play a significant role on the conversion accuracy. Based on this, a new loop filter topology with four poles and two zeros is proposed and compared to existing loop filters. This reveals that the proposed loop filter can yield more energy-efficient noise-shaping SAR ADCs than the ones seen in the literature today.

In three-dimensional integrated circuit (3D IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to/from TSVs. In Analog/Mixed signal ICs, the TSV coupling effect can cause coupling noise disturbance and degrades the performance of sensitive analog devices. In this paper, two different stacking integrations for the sensor array and the 3D IC, are considered and compared. In the face-up stacking integration, the transducers' flip chip bonded pads are directly bonded to the integrated circuit. In facedown integration type, however, the connections from the sensor output signal to the front end electronics is done via the TSVs. The TSV coupling noise is compared for the two schemes using the existing TSV coupling noise model. To validate the impact of stacking integration on the coupling noise, an ADC case study was designed and implemented using 130nm device technology and Tezzaron TSV technology. The simulations results show that the face-up integration could suppress the coupling noise by 10db. Moreover, a 23% reduction in footprint is achieved in this stacking integration.

Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact.

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The conditionVsb> 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, asVsb> 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

In this paper, we present the analysis and design of a self-biased single-ended charge sampling amplifier (CSA) in 90nm CMOS for catheter based intravenous ultrasound imaging applications. The proposed CSA is based on a 1V single-ended CMOS inverter-based cascode amplifier. The amplifier achieves a DC gain of 43.7 dB and a unity gain frequency of 1.37 GHz at a power consumption of 385 μW at 37°C - nominal temperature of human body with typical-typical (TT) models defined in the 90nm CMOS technology used for this design. Performance of the self-biased CSA is studied by connecting a single Capacitive Micro machined Ultrasound Transducer (CMUT) to it.

In this paper we present a simple analytical model for the estimation of signal-to-noise ratio (SNR) due to clock jitter for a general charge sampling amplifier. The proposed analytical model is compared with a previously published more complex model. Finally, we compare charge sampling and voltage sampling in terms of SNR due to clock jitter