EDBT 2026 Demo / reviewers in the wild / expert
Douglas P. Wieland
dblp:60/3473
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 70% Electronic design automation · 30% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA architecture |
0.0 | 1 | 1998 | A Novel Predictable Segmented FPGA Routing Architecture · FPGA 1998 |
Reconfigurable computing and FPGAs
FPGA routing architecture |
0.0 | 1 | 1998 | A Novel Predictable Segmented FPGA Routing Architecture · FPGA 1998 |
Electronic design automation › physical design › routing › FPGA routing
segmented channel routing |
0.0 | 1 | 1998 | A Novel Predictable Segmented FPGA Routing Architecture · FPGA 1998 |
Reconfigurable computing and FPGAs
FPGA physical design |
0.0 | 1 | 1998 | A Novel Predictable Segmented FPGA Routing Architecture · FPGA 1998 |
Methods — techniques the papers use, named apart from their topics
segmented routing fabric design · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | A Novel Predictable Segmented FPGA Routing ArchitectureabstractIn the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays. Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance |
FPGA | 11 |