Massively parallel computers are implemented by means of modules at different packaging levels. This paper discusses a hierarchical node clustering scheme (HNC) for packaging a class of reconfigurable processor arrays called Polymorphic Processor Array (PPA) which uses circuit-switchingbased routers at each node to deliver a different topology at every instruction. The PPA family suffers from an unknown signal delay between arbitrary two nodes connected by the circuited-switched paths. This either forces the hardware clock to compromise to the worst signal delay or makes the software dependent on the system size. The use of the HNC scheme allows to obtain communication speed-up and automatic control, at the compiler level, over signal propagation delay.

This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed.>

A massively parallel fine-grained SIMD (single-instruction multi-data-stream) computer for machine vision computations is described. The architecture features a polymorphic-torus network which inserts an individually controllable switch into every node of the two-dimensional torus such that the network is dynamically reconfigurable to match the algorithm. Reconfiguration is accomplished by circuit switching and is achieved at fine-grained level. Using both the processor coordinate in the torus and the data for reconfiguration, the polymorphic-torus achieves solution time that is superior or equivalent to that of popular vision architectures such as mesh, tree, pyramid and hypercube for many vision algorithms discussed. Implementation of the architecture is given to illustrate its VLSI efficiency.>

An interconnection network is presented for a massively parallel fine-grained single-instruction, multiple-data (SIMD) system, called the polymorphic-torus, whose design goal is to provide high communication bandwidth under a packaging constraint. This goal is achieved by the polymorphic principle, which injects switches with circuit-switching capability into every node of a base network (e.g. a two-dimensional torus). The polymorphic approach maintains wiring complexity of the base network but effectively increases the communication bandwidth due to its flexibility in reconfiguring the switches individually and dynamically to match the algorithm graph. Formal analysis on interpackage wiring (the flux) and the intrapackage wiring (the fluid) is given for the polymorphic-torus and the related torus networks. Three algorithms, namely, the Boolean, the max/min, and the sum operations, are developed to illustrate the use of the polymorphic principle in enhancing the communication bandwidth with no penalty of the interpackage wiring complexity.>

A parallel algorithm is presented for labeling the connected components of multicolored digital images. The algorithm takes advantage of the bottom-up divide-and-conquer strategy applied in tree and pyramid architectures but only requires a mesh topology. To support nonlocal communication, where meshes perform poorly, the authors propose the polymorphic torus, a regular mesh interconnection network in which each node is able to dynamically interconnect its ports, depending on its own data. By having each node properly drive such an interconnection, communication links between processors get established and disconnected and, as a result, the effective network diameter is reduced. The proposed connected-component labeling algorithm requires O( square root n) steps for a square root n* square root n multicolored image of an n-processor polymorphic torus, which is the same performance achieved in a tree architecture with 2n-1 processors. The lower number of processors and the simpler topology of polymorphic torus (vs. tree) make it a very suitable approach to mesh augmentation for intermediate-level vision applications.>

The recently developed Fast Hough Transform algorithm [3,4] alleviated the traditional exponential growth in computing complexity and storage of the Hough transform at a factor of several orders of magnitude thus enlightened the possibility of serving as a fundamental algorithm for multidimensional signal processing. This paper investigates its implementation on SIMD architectures consisting of a large number of identical bit-serial processing elements.

A recently-developed system simulation environment for multiple resource systems is described. The simulation tool integrates the description and simulation of software objects, hardware objects, interconnection topologies and user applications. In this study, a distributed operating system, which cooperatively manages the activity of multiple processors; a VLSI-oriented floating point signal processor; a shared memory architecture; and an application data flow graph [1] are investigated.