Demo Data from EDBT 2026 / reviewers in the wild / expert
T. Ericsson
dblp:60/4478
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% Hardware accelerators and domain-specific architectures · 38% Interconnection networks and networks-on-chip · 12% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
image processing accelerator |
0.0 | 1 | 1983 | LIPP-A SIMD Multiprocessor Architecture for Image Processing · ISCA 1983 |
Processor architecture and microarchitecture › SIMD
SIMD processor |
0.0 | 1 | 1983 | LIPP-A SIMD Multiprocessor Architecture for Image Processing · ISCA 1983 |
Processor architecture and microarchitecture
SIMD |
0.0 | 1 | 1983 | LIPP-A SIMD Multiprocessor Architecture for Image Processing · ISCA 1983 |
Methods — techniques the papers use, named apart from their topics
distributed processor topology · 0.0bit-serial processing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | LIPP-A SIMD Multiprocessor Architecture for Image ProcessingabstractLIPP (Linköping Image Parallell Processor) is a multiprocessor system intended mainly for image analysis and image processing but even other computing tasks where large amount of data should be manipulated in forms of matrices, such as weather forecasts or other related problems namely systems of differential equations. The processors within the processor array are of bit-serial type with the capability of directly processing data with wordlengths in the range of 1 bit to 32 bits in one bit increments without time penalty. Bit-serial operation gives the possibility of designing suprisingly fast algorithms. To each processor is a fairly large memory (64 Kbit) associated. A processor can instantly reach 8 neighboring memories through an interconnecting network. The processor array whose size is thought to be 16 by 16 it running in SIMD mode. In this way memory access collisions can be minimized. Image and matrix data are mapped in the memory space so that each memory holds a subimage. We call this mapping distributed processor topology. Because of the memory mapping and interconnection network neighborhood operations such as two dimensional convolution are easily performed. T. Ericsson, Per-Erik Danielsson |
ISCA | 1 |