This paper gives an insight into interdisciplinary research examining the use of Machine Learning techniques to monitor the vocal health of professional singers. The work reported establishes the viability of using a dataset of audio samples of the human voice to train a convolutional neural network to assess fluctuations in vocal performance of professional singers. Variations in the ease and quality of vocal production are a common experience among those who rely on their voice for a living, and vocal health issues can often prove traumatic and debilitating. Yet the use of data gathering and analysis among professional singers remains rare. The work reported in this study provides a novel basis for a method via which singers, and others who use their voice professionally, can make informed investigations into the potential causes of those fluctuations, and facilitate preventative medical intervention where appropriate.

The newly proposed Leaky Sign Regressor Least Mean Fourth (LSRLMF) algorithm is used in a fixed-point interference canceller for ElectroCardioGram (ECG) Baseline Wander (BW) removal application. An upper bound for the LSRLMF algorithm step-size is also presented. The LSRLMF-based interference canceller is quantized using different types of loss of precision methods. Through rigorous simulations, the quantization bit depth required for the different parameters of the LSRLMF-based interference canceller is found to be 9-bits for the most effective ECG baseline wander removal.

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation, and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a hardware description language (HDL)-based modeling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit's invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit cyclic redundancy check (CRC) circuit. The system modeled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems.

The weak signal levels experienced at the reception of the messages transmitted by navigation satellites, makes Global Positioning System (GPS) vulnerable to unintentional and intentional interference. This calls for appropriate modelling of GPS signal sources and jammers to assess the anti-jamming and interference mitigation capabilities of algorithms developed to be implemented for GPS receivers. Using a practical simulation model, this work presents an anti-jamming technique based on a novel algorithm. A fully adaptive lattice based notch filter is presented that provides better performance when compared to existing adaptive notch filter based techniques, chosen from the literature, in terms of convergence speed whilst delivering superior performance in the excision of the interference signal. To justify the superiority of the proposed technique, the noise and interference signal power is varied for in a wide dynamic range assessing jamming-to-noise density versus effective carrier-to-noise density performance at the output of the correlator.

Energy plays an important role in NFC passive tags as they are powered by radio waves from the reader. Hence reducing the energy consumption of the tag can bring large interrogation range, increase security and maximizes the reader's battery life. The ISO 14443 standard utilizes Manchester coding for the data transmission from passive tag to the reader in the majority of the cases for NFC passive communications. This paper proposes a novel method of Manchester encoding using the adiabatic logic technique for energy minimization. The design is implemented by generating replica bits of the actual transmitted bits and then flipping the replica bits, for generating the Manchester coded bits. The proposed design was implemented using two adiabatic logic families namely; Positive Feedback Adiabatic Logic (PFAL) and Improved Efficient Charge Recovery Logic (IECRL) which are compared in terms of energy for the range of frequency variations. The energy comparison was also made including the power-clock generator designed using 2-stepwise charging circuit (SWC) with FSM controller. The simulation results presented for 180nm CMOS technology at 1.8V power supply shows that IECRL shows approximately 40% less system energy compared to PFAL family.

In this paper a novel pipelining approach applicable to Winograd Fourier transforms is presented. The novel approach makes use of reconfigurable multiplier blocks to implement the real multipliers required for the transform as well as sharing the hardware resources among additions. The additions are realized using modified forms of butterfly circuits. The novel approach is tested on a 5-point Winograd Fourier transform and the circuit area and power dissipation of the design are estimated using an in-house power estimation tool and compared to the state-of-the-rt approaches.

This paper describes a fast and reliable mobile phone Android application platform for blood image analysis and malaria diagnosis from Giemsa stained thin blood film images. The application is based on novel Annular Ring Ratio Method which is already implemented, tested and validated in MATLAB. The method detects the blood components such as the Red Blood Cells (RBCs), White Blood Cells (WBCs), and identifies the parasites in the infected RBCs. The application also recognizes the different life stages of the parasites and calculates the parasitemia which is a measure of the extent of infection.

In this study, a novel hardware efficient digital ultrasound beamformer using single-bit second-order Σ-Δ modulators incorporated with band-pass decimation filters is presented. Beside the reduced size, cost and power consumption of the phased array front-end circuitry, there are significant image artifacts introduced by Σ-Δ beamformers. The elevated noise floor due to the repeated samples in dynamic focusing is greatly reduced by hardware efficient band-pass filters in the decimation stage following the beam summation. The B-scan images using experimental phantom data have shown that the proposed structure achieves significant improvements over the image resolution constructed by a conventional Σ-Δ beamformer. This novel structure ensures high quality B-scan images by preserving the hardware simplicity of the conventional single-bit Σ-Δ beamformers.

A new CMOS DC level shifter that can be programmed at a level less than the threshold voltage of a MOSFET is proposed. This design technique utilizes a bulk- driven MOSFET, which is biased with a constant reverse voltage, to shift the input. Furthermore since the proposed block is in a class-AB super source follower form, it is power- efficient. This paper presents the design and the simulation of the proposed block and also its application in a simple current mirror using a 0.35μm CMOS process, which indicates leading to the reduction of the voltage headroom consumption of the input device but without introducing DC offset current, while the additional distortion remain negligible until 1MHz operation. The additional static current consumption is as small as 5μA.

This paper describes a novel idea to identify the total number of red blood cells (RBCs) as well as their location in a Giemsa stained thin blood film image. This work is being undertaken as a part of developing an automated malaria parasite detection system by scanning a photograph of thin blood film in order to evaluate the parasitemia of the blood. Not only will this method eliminates the segmentation procedures that are normally used to segment the cells in the microscopic image, but also avoids any image pre-processing to deal with non uniform illumination prior to cell detection. The method utilizes basic knowledge on cell structure and brightness of the components due to Giemsa staining of the sample and detects and locates the RBCs in the image.

In this paper we propose a novel receiver for multiple input single output channels. Such approaches are preferred in boosting the diversity within the channel, to combat fading. Our receiver performs a space time block coding technique by making use of a blind algorithm, which is the constant modulus algorithm. Being a blind receiver, no training data streams are required to identify and to equalize the frequency selective communication channel. Different from the state-of-the-art techniques in the literature proposed for the channels with transmit diversity, the channel estimation and channel equalization are implemented all in one receiver without any need for an extra step to perform any one of these two. Furthermore, the receiver was designed by also considering a feedback filter in its equalizer for a better error rate performance. Step by step derivation of our novel receiver is shown in this paper alongside the simulation section, where the performance of our novel receiver is illustrated.

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

A voltage buffer so-called the bulk-driven flipped voltage follower is presented. This proposal is based on the flipped voltage follower (FVF) technique, but a bulk-driven MOSFET with the replica-biased scheme is utilized for the input device to eliminate the DC level shift. The proposed buffer has been designed and simulated with a 0.35 mum CMOS technology. The input current and capacitance of our proposal are 1.5 pA and 9.3 fF respectively, and with 0.8 V peak-to-peak 500 kHz input, the total harmonic distortion is 0.5% for a 10 pF load. This circuit can operate from a single 1.2 V power supply and consumes only 2.5 muA.

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures.

This paper provides an overview of the sources and effects of the RF impairments limiting and rendering the performance of the future wireless communication transceivers costly as well as hindering their wide-spread use in commercial products. As transmission bandwidths and carrier frequencies increase effect of these impairments worsen. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments in terms of bit-error-rate and image rejection ratio. The paper also give highlights of the various aspects of the research carried out in mitigating the effects of these impairments primarily in the digital signal processing domain at the baseband as well as providing low-complexity hardware implementations of such algorithms incorporating a number of power and area saving techniques

Global navigation satellite system (GNSS) receivers require solutions that are compact, cheap and low-power, in order to enable their widespread proliferation into consumer products. Furthermore, interoperability of GNSS with non-navigation systems, especially communication systems will gain importance in providing the value added services in a variety of sectors, providing seamless quality of service for users. An important step into the market for Galileo is the timely availability of these hybrid multi-mode terminals for consumer applications. However, receiver architectures that are amenable to high-levels of integration will inevitably suffer from RF impairments hindering their easy widespread use in commercial products. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments and develops algorithms that can compensate for them in the DSP domain at the base band with complexity-reduced hardware overheads, hence, paving the way for low-power, highly integrated multi-mode GNSS receivers

This paper details the development of an enhanced accuracy tonality index for Δ-Σ modulators that use Psychoacoustic techniques. This tonality measure is especially relevant for quantifying Δ-Σ modulators for performance of audio applications where the output spectra contain low amplitude tones. This tonality index is very useful for the design and evaluation of Δ-Σ modulators circumventing the need to build a modulator prototype and undertake detailed listening tests.

2006 17th British Machine Vision Conference, BMVC 2006 --

This paper presents a room equalization method based on iterative simple complex smoothing of measured acoustic impulse responses. This is useful in cases of long duration impulse responses. Corresponding time reduced impulse responses are derived which conform to perceptual principles. The smoothed impulse responses are then used to design equalization filters. Results from an audio-conferencing reverberant room using objective and subjective tests show that we can improve the measured and perceived quality of audio reproduction

To dramatically reduce the need for silicon reproduction due to poor noise performance, a close-loop simulation platform that combines both measured and/or simulation results of open-loop PLL sub-blocks has been developed. The platform is suited for Delta-Sigma based fractional-N frequency synthesizers enabling integrated circuit designers to directly meet cost, performance and schedule milestones. Case studies employing the developed platform are provided for a fractional-N frequency synthesizer operating near 5 GHz. The effects of dead-zone, dithering, near-integer divisor operation, noise folding and prescaler usage on the overall phase noise performance of the entire frequency synthesizer are detailed

In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50 % for 32-PSK and 37-58 % for 64-QAM modulated signals

This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (VT0+ 3VDSsat) to the maximum allowed for the CMOS process, as well as preventing latch-up

This paper presents a high-speed, low-power trace-back memory structure for a Viterbi decoder. The new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The trace-back memory is internally interleaved such that high-speed characteristic is achieved while low-power consumption is maintained. The structure is used together with appropriate clock and power-aware control signals. The design is 100% portable and is suitable for a SoftIP approach. Based on the AMS 0.35 mum CMOS implementation the trace-back memory is estimated to consume energy of 232 pJ, which is 53.6% less than a conventional RAM based design, with a maximum throughput of 1.1 Gbps

This paper describes an MPEG (moving pictures expert group) audio layer II - LFE (lower frequency extension) bit-stream processor targeting DAB (digital audio broadcasting) receivers that will handle the decoding of the frames in a computationally efficient manner to provide a synthesis sub-band filter with the reconstructed sub-band samples. Focus is given to the frequency sample reconstruction part, which handles the re-quantization and re-scaling of the samples once the necessary information is extracted from the frame. The comparison to a direct implementation of the frequency sample reconstruction block is carried out to prove increased computational efficiency

The aim of this paper is to determine the stability of higher-order Delta-Sigma modulators using the describing function method. The maximum stable input limits for third-, fourth- and fifth-order Chebyshev Type II based Delta-Sigma modulators are established. These results are useful for optimising the design of higher-order Delta-Sigma modulators

In this paper, a technique and method is presented to suppress the effect of clock-jitter in continuous-time delta-sigma modulators with switched-current (current-steering) digital to analogue converters. A behavioural, transistor-level and noise analysis are presented followed by circuit-level simulations. The proposed approach which is a switched-current type of digital to analogue conversion is fully compatible with CMOS processes and multi-bit operations which are widely used in high speed applications. Moreover, having a pulse-shaped output signal does not introduce extra demands on the modulator and hence does not increase the modulator's power consumption. A third-order continuous-time DeltaSigma modulator with the proposed digital-to-analogue converter in its feedback was used for circuit-level simulations. Results proved the robustness of the technique in suppressing the clock-jitter effects

A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (times2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (times2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35mum CMOS technology

An adaptive self-calibrating image rejection receiver is described, containing a modified weaver image rejection mixer and a digital image rejection processor (DIRP). The blind source-separation-based DIRP eliminates the I/Q errors improving the image rejection ratio (IRR) without the need for trimming or use of power-hungry discrete components. Hardware complexity is minimal, requiring only two complex-coefficients; hence it can be easily integrated into the signal processing path of any receiver. Simulation results show that the proposed approach achieves 75-97 dB of IRR.

To avoid the bias in the equation error (EE) method, the unit norm constrained EE approach was introduced. In order to get faster convergence, the implementation of the EE with the unit norm constraint using recursive least squares via variable loading is presented.

The paper presents the results of the "Virtual Classroom" project sponsored by the University of Westminster, Educational Initiative Centre (EIC) for delivering lectures online. The ultimate aim was to provide a portable hardware and easy to use software toolset as well as easy to follow guidelines on how to propel the lectures from the conventional dull chalk and talk environment to the realm of all interactive computer assisted Web based electronic classroom. The additional goal was to minimise the number of staff required to give the lectures and allow them to use their valuable time for other academic duties. The proposed hardware/software setup is a fully automatic solution controllable from a single PC. It allowed full student interaction and use of multimedia in the lecture. Although the best quality was achieved by use of multicasting, the students connecting via modem can also take interactive part in the lectures.

Phase and gain mismatches between the I and Q analog signal processing paths of a quadrature receiver are responsible for the generation of image signals which limit the dynamic range of a practical receiver. We analyse the effects of these mismatches and propose a low-complexity blind adaptive algorithm to minimize this problem. The proposed solution is based on two, 2-tap adaptive filters, arranged in an adaptive noise canceller (ANC) set-up. The algorithm lends itself to efficient real-time implementation with minimal increase in modulator complexity.

Two novel effective-fourth-order (eighth-order) resonator based MASH (MultistAge noise SHaping) bandpass /spl Sigma/-/spl Delta/ modulators are introduced at the behavioural level and subsequently examined by simulations utilising the ALTA SPW environment. The considered bandpass configurations have in their loop filter a cascade of standard second-order resonator structures in order to achieve appropriate noise shaping. The quantisation noise in each stage is suppressed by feeding the error of each section into the input of the following stage. It is demonstrated in this paper that the quadruple effective-first-order cascade configuration has significantly better performance as well as conforming more closely with theory in comparison with the effective-second-order effective-second-order cascade. The superior performance of the former can be attributed to the cumulative effect of the multi-bit outputs as well as the presence of more notch filters.

This paper addresses a new approach for the design of multiband filters with step like magnitude responses and extremely flat, weighted passbands down to /spl mu/dBs. Our new technique can also be used for the multiband stepwise approximation of arbitrary filter magnitude responses with precise transition band control. One marked advantage of the technique is that our basic building blocks are the modified polyphase (W) filters. The points of transition from one flat-top to another, namely the multiple transition bands of our filter are completely free of cross-over oscillations. One other advantage of this technique is that we are not confined to employing IIRs only. To this end perfect reconstruction FIR filters can also be used. In both the FIR and IIR cases our technique is general purpose and works for both real and complex valued filter coefficient cases.

We propose a novel technique for the design of low-order infinite impulse response (IIR) filter models of head-related transfer functions (HRTFs) that uses balanced model truncation. We design tenth-order IIR filters, suitable for efficient real-time implementation, from preprocessed HRTF impulse responses that are of significantly superior quality to current IIR models derived with the Prony and Yule-Walker methods.

In this paper two powerful methods of FIR-to-IIR filter order reduction are presented and compared: truncation of balanced model and Hankel-norm optimal approximation. Conclusions based on very many filter order reduction runs indicate that balanced model truncation is often preferrable.>

This paper reports on establishing a good starting point for a half-band fixed-point polyphase filter design technique, which employs a natural algorithm, when fifth and seventh order filter structures are used. It should be noted that the convergence of combinatorial algorithms is sensitive to initial conditions implying that the seed filter coefficients and search space for subsequent filters need to be chosen with care for the algorithm to converge efficiently. This requires the definition of a bounded area and bounded volume in the coefficient space for the fifth and seventh order filters respectively. This will ensure that the zeroes are on the unit circle, and hence, will result in maximum null depths being achieved at the zero frequencies (as is the case with the elliptic approximation).>

This paper presents a design technique for high fidelity multistage decimation filters based on polyphase and decimator structures, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 15 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit flipping algorithm". This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to other approximation methods. The coefficients and frequency responses of the cascaded filter are reported.>