Design reuse is expected to be a key enabler for system designs in the 90's. Proponents claim that design reuse increases competitiveness through better quality, improved predictability and better productivity. On the other hand, skeptics say that design reuse is not realizable due to several barriers including rapid changes in technology, lack of standardized libraries and the presence of human, as opposed to technical barriers. Is design reuse a reality? How much is reused in practice? Where is it most applicable? Do concrete metrics exist for reusability? The panel will assess the track record of design reuse and discuss its status and future.

A two-dimensional channel routing program for hierarchical IC layout with orthogonal building blocks of variable size and shape is presented. A two dimensional channel model and a one layer channel router are used. A detailed description of the routing scheme which avoids the generation of “switch box” problems is given. The behavior of the two-dimensional routing algorithm to single and coupled channel intersections is demonstrated.

This paper presents a new algorithm for the initial placement of hierarchical VLSI circuits. The components to be placed are orthogonal macrocells of variable shape and size. This algorithm combines the advantages of force directed placement and min-cut algorithm. It provides an initial placement which avoids overlapping between cells and includes an estimation of routting area. This algorithm is suitable for regular cell arrangements, too.