Vertical interconnects used in monolithic 3-D integrated circuits (3-D ICs), so-called monolithic interlayer vias (MIVs), are as small as local vias. Thus, redesigning an existing 2-D IC layout in a monolithic 3-D IC generally results in shorter wire length than the 2-D IC layout. In addition, MIVs have almost negligible resistance and capacitance, so their impact on signal delay is very small. Thus, redesigning a 2-D IC layout in a monolithic 3-D IC is expected to improve its performance significantly. Some researchers designed several monolithic 3-D IC layouts and showed their timing benefits in the literature. In this paper, we present analytical models for performance (timing) benefits of multitier gate-level monolithic 3-D ICs. The analytical models we develop in this paper can be used to quickly estimate the performance benefits multitier gate-level monolithic 3-D integration provides without physically redesigning 2-D IC layouts in 3-D.

We introduce dynamic watermarking techniques for protecting the value of intellectual property of CAD and compilation tools and reusable design components. The essence of the new approach is the addition of a set of design and timing constraints which encodes the author's signature. The constraints are selected in such a way that they result in a minimal hardware overhead while embedding a unique signature that is difficult to remove and forge. Techniques are applicable in conjunction with an arbitrary behavioral synthesis task such as scheduling, assignment, allocation, transformation, and template matching.On a large set of design examples, studies indicate the effectiveness of the new approach that results in signature data that is highly resilient, difficult to detect and remove, and yet is easy to verify and can be embedded in designs with very low hardware overhead. For example, the probability that the same design with the embedded signature is obtained by any other designers by themselves is less than 1 in 10 102 , and no register overhead was incurred. The probability of tampering, the probability that part of the embedded signature can be removed by random attempts, is shown to be extremely low, and the watermark is additionally protected from such tampering with error-correcting codes.

Summary and Conclusions -A novel methodology is proposed for designing fault-tolerant real-time multi-processor systems-on-a-chip to achieve optimal productivity. The methodology employs the heterogeneous built-in-self-repair (BISR) based on graceful degradation and yield enhancement techniques as an embedded optimization engine. The technique exploits the flexibility provided in task-level scheduling and algorithm selection steps. A hardware fault model is developed for modern super-scalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals. For the first time, heterogeneous BISR is used at the task level. The key idea is to adapt scheduling and algorithm selection to the available nonfaulty resources. If there is a fault in memory, the algorithms that use less memory are selected and the scheduler exploits the other abundant resource, viz, the processors, more vigorously to compensate for the loss of part of memory. Similarly, a fault in a processor is backed up by memory. The synthesis approach minimizes the degradation in performance for single or multiple faults using simulated annealing-based algorithm selection, scheduling, and assignment algorithms. On the large set of examples this adaptive algorithm selection and scheduling technique has achieved important improvement of throughput compared to conventional nonadaptive schemes. The experimental results also indicate that important improvement in productivity can be achieved by using the extra throughput gained from the technique.

Symbolic debuggers are system-development tools that can accelerate the validation speed of behavioral specifications by allowing a user to interact with an executing code at the source level. In response to a user query, the debugger must retrieve and display the value of a source variable in a manner consistent with user expectations with respect to the source statement where execution has halted. However, when a behavioral specification has been optimized using transformations, values of variables may either be inaccessible in the runtime state or inconsistent with user expectations. We address the problem that pertains to the retrieval of source values for the globally optimized behavioral specifications. We present a new approach for symbolic debugging. The implementation of the new debugging approach poses several optimization tasks. We formulate the optimization tasks and develop heuristics to solve them. We demonstrate the effectiveness of the proposed approach on a set of designs.

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1 The economic viability of the reusable core-based design paradigm depends on the development of techniques for intellectual property protection. We introduce the first dynamic watermarking technique for protecting the value of intellectual property of CAD and compilation tools and reusable core components. The essence of the new approach is the addition of a set of design and timing constraints which encodes the author's signature. The constraints are selected in such a way that they result in minimal hardware overhead while embedding the signature which is unique and difficult to detect, remove and forge. We establish the first set of relevant metrics which forms the basis for the quantitative analysis, evaluation, and comparison of watermarking techniques. We develop a generic approach for signature data hiding in designs, which is applicable in conjunction with an arbitrary behavioral synthesis task, such as scheduling, assignment, allocation, and transformations. Error correcting...

This paper addresses an optimal technique for throughput optimization of general non-linear data flow computations using a set of transformations. Throughput is widely recognized as the most important design metric of the modern DSP and communication applications. Numerous approaches have been proposed for throughput optimization, but most were restricted to limited classes of computations. They have limited effectiveness when applied to large complex non-linear DSP and communication computations. The new technique is used as an optimization engine in a divide-and-conquer global approach for throughput optimization. We demonstrate the effectiveness of the new technique on numerous real-life non-linear designs.

The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We developed the design methodology for the low-power core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrial strength multimedia and communication applications.

We introduce an approach for power optimization using a set of compilation and architectural techniques. The key technical innovation is a novel divide-and-conquer compilation technique to minimize the number of operations for general computations. Our technique optimizes not only a significantly wider set of computations than the previously published techniques, but also outperforms (or performs at least as well as other techniques) on all examples. Along the architectural dimension, we investigate coordinated impact of compilation techniques on the number of processors which provide optimal trade-off between cost and power. We demonstrate that proper compilation techniques can significantly reduce power with bounded hardware cost. The effectiveness of all techniques and algorithms is documented on numerous real-life designs.

Functional debugging of application specific integrated circuits (ASICs) has been recognized as a very labor-intensive and expensive process. We propose a new approach based on the divide and conquer optimization paradigm for the functional test pattern execution. The goal is to maximize the simultaneous controllability of an arbitrary set of the user selected variables in the design at the debugging time for facilitating the functional test pattern execution while minimizing the hardware overhead. The approach imposes minimal restriction on register sharing so that the synthesized designs will have the desired characteristic while minimizing the additional hardware overhead and minimizing the disruption of the optimization potential when scheduling, allocation and binding tasks in high-level synthesis are performed. The effectiveness of the proposed approach is demonstrated on a number of designs.

We propose a novel methodology for designing fault-tolerant real-time system to achieve optimal productivity on a single-chip multiprocessor platform using the heterogeneous built-in-self-repair (BISR) based graceful degradation and yield enhancement technique as an embedded optimization engine which exploits task-level scheduling and algorithm selection flexibility. We also developed a hardware fault model for modern superscalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals.

The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. We develop the design methodology for the low power core-based real-time system-on-chip based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which result in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the non-preemptive scheduling heuristic which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrial-strength multimedia and communication applications.

Numerous watermarking-based techniques for intellectual property protection of DSP artifacts, such as images, compressed and uncompressed audio and video data, and text documents have been proposed. However, the applicability of all techniques proposed until now are limited to digital data and they either implicitly or explicitly exploit the imperfection of human perception to audio and video. We propose the first watermarking technique for protecting the intellectual property of DSP designs. The essence of the technique is the use of additional synthesis constraints to encode the authorship signature. The constraints are selected in such a way that they result in minimal hardware overhead while embedding the signature which is unique and difficult to detect and remove. The technique is applicable to all levels of design process, from the algorithm, system and behavioral synthesis to logic synthesis and physical design levels. The technique is illustrated on a set of DSP design examples on all levels of the design process.

We consider the problem of schtifing the mixed worMoad of both sporadic (on-fine) and periodic (off-fine) tasks on variable voltage processor to optimize power consumption while ensuring that ~ periodic tasks meet their destines and to accept as many sporadic tasks, which can be guaranteed to meet their destines, as possible.The proposed efficient dgonthms restit in the scheduling solutions, which are very close to the minimum bound achievable with the dynamictiy variable voltage approach.The effectiventis of the proposed dgonthrns is shown on extensive experiments with rd-fife design examples.

The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. We describe the synthesis of systems-on-a-chip based on core processors, while treating voltage (and correspondingly the clock frequency) as a variable to be scheduled along with the computation tasks during the static scheduling step. In addition to describing the complete synthesis design flow for these variable voltage systems, we focus on the problem of doing the voltage scheduling while taking into account the inherent limitation on the rates at which the voltage and clock frequency can be changed by the power supply controllers and clock generators. Taking these limits on rate of change into account is crucial, since changing the voltage by even a volt may take time equivalent to 100 s to 10000 s of instructions on modern processors. We present both an exact but impractical formulation of this scheduling problem as a set of nonlinear equations, as well as a heuristic approach based on reduction to an optimally solvable restricted ordered scheduling problem. Using various task mixes drawn from a set of nine real life applications, our results show that we are able to reduce power consumption to within 7% of the lower bound obtained by imposing no limit at the rate of change of voltage and clock frequencies.

Successive, well organized application of transformations has beenwidely recognized as an exceptionally effective, but complex anddifficult CAD task. We introduce a new potential-driven statisticalapproach for ordering transformations. Two new synthesis ideasare the backbone of the approach. The first idea is to quantifythe characteristics of all transformations and the relationship betweenthem based on their potential to reorganize a computationsuch that the complexity of the corresponding implementation isreduced. The second one is based on the observation that transformationsmay disable each other not only because they prevent theapplication of the other transformation, but also because both transformationstarget the same potential of the computation. These twoobservations drastically reduce the search space to find efficient andeffective scripts for ordering transformations. A key algorithmicnovelty is that both conceptual and optimization insights as well asall optimization algorithms are automatically derived by organizedexperimentation and statistical methods. On a large set of diversereal-life examples improvements in throughput, area, and power bylarge factors have been obtained. Both qualitative and quantitativestatistical analysis indicate effectiveness, high robustness, and consistencyof the new approach for ordering transformations.

Reduction of the number of operations optimizes the important design metrics such as area, cost, throughput, and power consumption for both custom ASIC and programmable processor implementations. We propose a novel technique to minimize the number of operations in DSP computations. The first step of the approach logically partitions a computation into strongly connected components. The second step optimizes each component separately. In the third step the components are merged to further optimize. Finally, the components are scheduled to minimize memory consumption. The effectiveness of our approach is demonstrated on real-life examples.

Although the undeniable importance of high quality, efficient and effective DSP synthesis benchmark has been firmly and widely established, until now the emphasis of benchmarking has been restricted on assembling individual examples. In this paper we introduce the "ideal candidate benchmark methodology" which poses the development of the benchmark as well as defines a statistical and optimization problem. We first outline the goals and requirements relevant for the benchmark development. After discussing the computational complexity of the benchmark selection problem, we present a simulated annealing-based algorithm for solving this computationally intractable optimization task. Using this approach from 150 examples we select 12 examples for the new DSP Quant benchmark for DSP hard Real-Time applications. The DSP benchmark is statistically validated, and its application to the analysis and development of system-level synthesis algorithms is demonstrated,.

We develop an approach to minimizing power consumption of portable wireless DSP applications using a set of compilation and architectural techniques. The key technical innovation is a novel divide-and-conquer compilation technique to minimize the number of operations for general DSP computations. Our technique optimizes not only a significantly wider set of computations than the previously published techniques, but also outperforms (or performs at least as well as other techniques) on all examples. Along the architectural dimension, we investigate coordinated impact of compilation techniques on the number of processors which provide optimal trade-off between cost and power. We demonstrate that proper compilation techniques can significantly reduce power with bounded hardware cost. The effectiveness of all techniques and algorithms is documented on numerous real-life designs.

While numerous power optimization techniques have been proposed at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-electronic subsystems, such as disks, has not been addressed. We propose a conceptually simple, but realistic power consumption model for disk drives. We present heuristics for optimization of power consumption in several common hard real-time disk-based design systems. We show how to coordinate task scheduling and disk data assignment, in order to minimize power consumption in both electronic and mechanical components of used disks. Extensive experimental results indicate significant power reduction.