A problem of deadlock avoidance in store-and-forward networks with at least two buffers per node is considered for fixed as well as dynamic routing. For both cases polynomial time, centralized deadlock avoidance algorithms are proposed and shown to be optimal in a sense of possible buffer utilization. When the number of buffers is equal to one for each node the problem is known to be NP-complete, thus, unlikely to admit a polynomial-time algorithm. The presented results may be also interesting for other applications, some massively parallel computer systems being one of the examples.>

Abstract Store‐and‐forward communication networks may be designed so as to be free from store‐and‐forward deadlock. This is accomplished by incorporating in the network an acyclic buffer graph on which messages are forwarded, from buffer to buffer, according to all the desired routes. A technique producing minimum buffer graphs for a rather large class of networks is illustrated. Successively, a comparison is made with other well‐known deadlock avoidance techniques, showing that substantial savings can be achieved.

An important parameter related to the efficiency of algorithms for data transmission on SS/TDMA systems is the number of switching modes they generate. It is shown in this note that time-optimal algorithms produce the maximum number of switchings only if the transmission durationLis exponential inN, whereNis the number of channels. This result explains the good performance exhibited by those algorithms in several simulation results.

A flow control procedure for an acyclic store-and-forward network is introduced which uses only information local to each node and is deadlock-resistant (i.e., detects and recovers deadlock at a negligible cost). The procedure requires less than3n/2buffers (the exact value depending on the network topology), wherenis the number of nodes in the network. It is shown that this number is lower bound for distributed deadlock-resistant procedures. From a practical point of view, this means that a single buffer class is sufficient, provided that the exchange mechanism for input buffers is realized as a synchronized procedure between any two contiguous nodes (rather than as a purely local procedure). Some extension to more general networks are then proposed.

Directed graphs having logical control associated with each vertex have been introduced as models of computational tasks for automatic assignment and sequencing on parallel processor systems. A brief review of their properties is given. A procedure to test the “legality” of graphs in this class is described, and leads to algorithms for counting the number of all possible executions (AND-type subgraphs), and for evaluating the probability of ever reaching a given vertex in the graph. Numerical results are given for some example graphs.

A dynamic memory allocation algorithm is presented making use of a priori information about a computer program. A two- level storage system is assumed, and a replacement algorithm is developed based upon a priori knowledge of interaction factors between any two space-taking entities associated with a computation.

An algorithm for allocation of memory resources is presented making use of a priori information about a computer program. This static allocation algorithm is based on a directed graph model of computations with particular attention to the memory allocation of programs assigned for execution on multiprocessor systems.