A micropower, low-noise, bandpass amplifier for biomedical implants is presented. Operating at low frequency, the amplifier is fully integrated without any external passive components. Low-frequency noise and offset is reduced through the autozeroing technique. The autozeroing frequency and noise bandwidth is optimized to reduce noise folding. The design consists of a novel variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. Subthreshold operation is utilized in all input pair transistors to reduce power consumption, while a low-Gm OTA (operational transconductance amplifier) is realized with a current division technique. A cross-couple parallel pair of source degeneration transistors is utilized to increase the linearity crucial to neural spike detection. The design is realized in a CMOS 0.18mum process. It has an offset of 600muV, a variable gain from 42dB to 0dB, and 50 to 900Hz bandwidth while occupying 0.245mm2area. The total circuit consumes only 26muW in a 1.8V power supply; the input referred noise is estimated to be 5.6muVrms.

A novel charge-metering stimulus amplifier is proposed for high performance neural prosthesis stimulation. The new charge-based approach with feedback has low charge error 0.5%, low charge imbalance 0.2%, and high power efficiency. Charge-metering stimulus amplifier can be implemented using advanced 0.18mum CMOS technology and is compatible with mixed-signal system-on-a-chip (SoC) implantable devices. It also has the capability to monitor the electrode-tissue contact quality and estimate the interface impedance in real-time for robust stimulation.

A multi-disciplinary project was described that is developing a microchip-based neural prosthetic for the hippocampus, a region of the brain responsible for the formation of long-term memories, and that frequently is damaged as a result of epilepsy, stroke, and Alzheimer's disease. The essential goals of this effort include: (1) experimental study of hippocampal neuron and neural network function; (2) formulation of biologically realistic mathematical models of neural system dynamics; (3) microchip implementation of hippocampal system models; and (4) hybrid neuron-silicon interfaces for bi-directional communication with the brain. By integrating solutions to these component problems, the team is realizing a microchip-based model of hippocampal nonlinear dynamics that can perform the same function as a removed, damaged hippocampal region. Through bidirectional communication with other neural tissue that normally provides the inputs and outputs to/from the damaged hippocampal area, the neural model can serve as a neural prosthesis. A proof-of-concept is presented in the context of an application to the hippocampal slice. How the current work in brain slices is being extended to behaving rats and primates also is described.

The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the first smart-memory devices designed to support virtual addressing and capable of executing multiple threads of control. In this paper, we describe the prototype PIM architecture. We emphasize three unique features of DIVA PIMs, namely, the memory interface to the host processor, the 256-bit wide datapaths for exploiting on-chip bandwidth, and the address translation unit. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we achieve an average speedup of 3.3X over host-only execution, due to lower memory stall times and increased fine-grain parallelism. These 1-PIM results suggest that a PIM-based architecture with many such chips yields significantly higher performance than a multiprocessor of a similar scale and at a much reduced hardware cost.

Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth requirements.The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect.DIVA increases memory bandwidth through two mechanisms: (1) performing selected computation in memory, reducing the quantity of data transferred across the processor-memory interface; and (2) providing communication mechanisms called parcels for moving both data and computation throughout memory, further bypassing the processor-memory bus.DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations.In this paper, we focus on several aspects of DIVA designed to effectively support such computations at very high performance levels: (1) the memory model and parcel definitions; (2) the PIM-to-PIM interconnect; and, (3) requirements for the processor-to-memory interface.We demonstrate the potential of PIMbased architectures in accelerating the performance of three irregular computations, sparse conjugate gradient, a natural-join database operation and an object-oriented database query.

The authors describe a formalism for the representation of interface behavior which can be used for high-level synthesis by a design automation system. The Design Data Structure can represent the many facets of interface behavior in a unified way, including timing constraints, synchronous and asynchronous signals, control flow, and data manipulation. Its descriptive power is more complete than some other formalisms in use, including event and annotated data-flow graphs. The representations described here can be used by data path synthesizers to capture more complex timing information than is typically handled and to separate control from data manipulation information to produce cleaner data flow graphs. The Design Data Structure has been used successfully as an internal representation for a natural-language interface for system specification.>

Noun phrases consisting of a sequence of nouns (sometimes referred to as nominal compounds) pose considerable difficulty for language analyzers but are common in many technical domains. The problems are compounded when some of the nouns in the sequence are ambiguously also verbs. The phrasal approach to language analysis, as implemented in PHRAN (PHRasal ANalyzer), has been extended to handle the recognition and partial analysis of such constructions. The phrasal analysis of a noun sequence is performed to an extent sufficient for continued analysis of the sentence in which it appears. PHRAN is currently being used as part of the SPAN (SPecification ANalysis) natural language interface to the USC Advanced Design AutoMation system (ADAM) (Granacki et al, 1985). PHRAN-SPAN is an interface for entering and interpreting digital system specifications, in which long noun sequences occur often. The extensions to PHRAN's knowledge base to recognize these constructs are described, along with the algorithm used to detect and resolve ambiguities which arise in the noun sequences.

This paper describes a natural language interface, PHRAN-SPAN, for specifying the abstract behavior of digital systems in restricted English text. A neutral formal representation for the behavior is described using the USC Design Data Structure. A small set of concepts that characterize digital system behavior are presented using this representation. Finally, an intermediate representation based on Conceptual Dependencies is presented. Its use with a semantic-based parser to translate from English to the formal representation is illustrated by a series of examples.

This paper describes ADAM, an integrated Advanced Design AutoMation system, with focus on the knowledge-based synthesis subsystem. Working parts of this subsystem include a number of design activities and utilities, and a unified, multidimensional, hierarchical design representation. Two aspects of the synthesis subsystem are described in detail: the design planner and the natural language interface. The planner builds a plan for synthesis and analysis activities, drawing inferences from a knowledge base represented by a semantic net. The natural language interface accepts system-level behavioral specifications. Both of these packages are currently being implemented.