Electronic system-level (ESL) design automation has been identified by Dataquest as the next productivity boost for the semiconductor industry. We have put together a distinguished panel of experts to discuss if we are ready for system-level synthesis.

Verilog HDL was a breakthrough for the hardware design community in 1986. Over the years, the methodology based on the Verilog HDL has been extended with utilities and enhancements. With 0.25- and 0.18 µ processes enabling a system to be packed onto a single integrated circuit (IC), design problems have surfaced that no one could have predicted 13 years ago. As a result, several new design language proposals have been introduced since the last Design Automation Conference (DAC), all claiming to aid system-on-chip (SOC) design. Several claim to improve the designer's ability to efficiently create, implement, and verify SOC designs from architectural specification through functional implementation.The panel, comprised of experienced designers and representatives of organizations submitting design language proposals, will debate the various proposals and will try to identify what future trend will accelerate system design.Questions and issues to be considered include:What's in store for the future — C, Java, Superlog, HDL or SLDL?A comparison of modeling, gate-level and behavioral simulation capabilities of a new design language to current languages/tools/methodsA comparison of the software development capabilities of a new design language to current languages/tools/methodsA review of the projected design environment of a new design language to current languages/tools/methods.

The need for increased performance at the high end of the Titan family of computers meant that the Ardent Computer Corp. had to bring to market a second-generation processor rapidly. Changes in four major areas were made to complete the second-generation Titan in less than one year. First, more aggressive ASIC technology was applied. Second, microarchitectural simplifications that greatly reduced the complexity of the design were identified. Third, more automatic schemes for generating functional (as opposed to manufacturing) tests were developed. last, logical synthesis was used extensively; over 80% of the gates in the final ASIC designs were synthesized. A review is presented of how changes in these four areas enabled the authors to deliver a processor with two times the performance of the first-generation processor at about the same cost.>

Much of the performance analysis done in designing a computer is based on fundamental operation rates, like cycle time and number of pipe stages in an operation pipeline. This kind of analysis yields peak computation rates which, in fact, may never be realized. Resource contention between different units, each of which has a fundamental operation rate adequate to support a given overall peak, may cause the actual obtainable rate to be much less. In order to determine the effects of interactions between different requestors and common resources, micro-analysis, or detailed modelling of the part of the system in question, is necessary. In this paper, we report on the results of such an analysis on the operation pipe of the Titan graphics supercomputer. The Titan is a new class of machine with a supercomputer-style architecture implemented in a technology appropriate for a single-user machine. The micro-analysis reported here resulted in enhancing the actual obtainable computation rate from 10.8 Mflops to 14.6 Mflops for a particular real application, while the fundamental operation rate is 16 Mflops.

No abstract available.

The Amdahl 580 processor is a pipelined processor whose performance can be affected by characteristics of the instructions it executes. This paper describes certain optimizations made to a set of system software routines during their development. The optimization effort was driven by the execution frequencies of common paths through the programs in question, and by the execution characteristics of those paths, as shown by a processor simulator. Path optimization itself was done with both general program optimization techniques and with techniques specific to the particular characteristics of the 580's pipeline. Overall, the average execution time for these routines was reduced by over 50%.

This paper reports the results of some measurements taken on the effects two new solid state paging devices, the STC 4305 and the Intel 3805, have on paging performance in the Michigan Terminal System at the University of Michigan. The measurements were taken with a software monitor using various configurations of the two solid state devices and the fixed head disk, which they replace. Measurements were taken both during regular production and using an artificial load created to exercise the paging subsystem. The results confirmed the expectation that the solid state paging devices provide shorter page-in waiting times than the fixed-head disk, and also pointed up some of the effects which their differing architectures have on the system.

A technique for simulating incomplete systems is given which allows performance prediction during system design. This technique, called integrated simulation, allows the system design to itself be a simulation model, thus avoiding the overhead of maintaining a separate, valid simulation model for the system. The paper presents integrated simulation in the framework of a system modeling language called the Program Process Modeling Language, PPML. This language provides a means for describing systems of concurrent processes in both abstract and explicit terms, thus lending itself well to a top-down design method. In the design process, any PPML representation of the system can be simulated directly, from the most abstract design to the completely elaborated system. Simulation of the completely elaborated system is, in fact, simply the system in execution. The paper defines PPML and describes the techniques required to simulate PPML systems given various underlying machines. It concludes with a discussion of the limitations of the integrated simulation method.