A growing number of applications rely on fast pattern matching to scan data in real-time for security and analytics purposes. The RegX accelerator in the IBM Power Edge of Network (PowerEN) processor supports these applications using a combination of fast programmable state machines and simple processing units to scan data streams against thousands of regular-expression patterns at state-of-the-art Ethernet link speeds. RegX employs a special rule cache and includes several new micro-architectural features that enable various instruction dispatch and execution options for the processing units. The architecture applies RISC philosophy to special-purpose computing: hardware provides fast, simple primitives, typically performed in a single cycle, which are exploited by an intelligent compiler and system software for high performance. This approach provides the flexibility required to achieve good performance across a wide range of workloads. As implemented in the PowerEN processor, the accelerator achieves a theoretical peak scan rate of 73.6 Gbit/s, and a measured scan rate of about 15 to 40 Gbit/s for typical intrusion detection workloads.

The transition to multicore architectures creates significant challenges for programming systems. Taking advantage of specialized processing cores such as those in the Cell BE processor and managing all the required data movement inside the processor cannot be done efficiently without help from the software infrastructure. Alongside new programming models and compiler support for multicores, programmers need performance evaluation and analysis tools. In this paper, we present tools that help analyze the performance of applications executing on the Cell platform. The performance debugging tool (PDT) provides a means for recording significant events during program execution, maintaining the sequential order of events, and preserving important runtime information such as core assignment and relative timing of events. The trace analyzer (TA) reads and visualizes the PDT traces. We describe the architecture of the PDT and present several important use cases demonstrating the usage of PDT and TA to understand the performance of several workloads. We also discuss the overhead of tracing and its impact on the benchmark execution and performance analysis.

A new approach for sampling rate conversion of digitally sampled signals is presented. The approach enables conversion from any given source sampling rate to any desired target sampling rate even if the source and destination clocks are not synchronous. The importance of algorithm is in a communication system where the sampling is done on one system and the playback is done on another, in such cases a drift between the clock occurs causing synchronization problems. The algorithm utilizes a very simple approach and indeed consumes less than one Mips. The algorithm was implemented on the IBM Signal Processor (Mwave-MDSP2780) and is used to convert a low sampling rate (8 or 9.6KHz) to the high CD rate (44.1Khz) and vice-versa.

The feasibility of using multi microphone noise cancellation techniques to enhance the performance of hearing aids was investigated in a project carried out by the IBM Israel scientific center. A short survey of some of the work in this field and a summary of the results and the motivation for the project will be given below, together with a description of an listening test which was carried out on the system. The results of the tests indicate that a marked improvement in intelligibility may be obtained using these techniques.