This work introduces a pseudo-dynamic design methodology for fully synthesizable standard-cell-based comparators, accompanied by a compact transistor-level model, in subthreshold region, for delay and power estimation. Two non-rail-to-rail input common-mode range (ICMR) topologies, implemented with AOI (and-or-invert) and OAI (or-and-invert) gates, are proposed. Compared with existing dynamic standard-cell-based comparators, the proposed designs achieve higher speed and lower power consumption, while remaining only marginally slower than the best-performing rail-to-rail solution at 150 mV. Post-layout simulations referring to a 45 nm CMOS process for supply voltages of 150 mV and 600 mV demonstrate that the proposed designs offer the best trade-off between delay, power, offset, and noise in ultra-low-voltage scenarios where rail-to-rail operation is not required.

Exploiting the recently introduced concept of the Dickson charge pump (CP) used as a signal amplifier, this paper introduces a new class of gain boosted amplifiers that can be obtained when the small-signal model of the charge transfer device depends on the input signal. The original design equations are enhanced, resulting in a new effective equivalent model for amplifiers based on CP circuits. The analytical predictions are validated by simulation and experimental results on a silicon prototype implemented in 65-nm standard CMOS technology.

This paper introduces a novel design approach and a prototype of a fully on-chip charge pump (CP)-based boost converter for integrated circuits powered by single solar cells. Measured performance proves the effectiveness of the proposed architecture and design strategy. Comparison with other integrated energy harvesting solutions based on CPs shows that the proposed solution occupies the lowest area with a comparable power conversion efficiency. Moreover, the power density is about 2.5 times higher than the best value reported.

This paper presents and discusses two Dickson charge pumps that are capable of working with a supply voltage lower than the MOS threshold voltage and are particularly suited for energy-constrained applications. Specifically, the paper includes a theoretical analysis of a previous topology introduced by the authors, and then it discusses a novel topology which solves drawbacks of the previous one. The paper also includes a comparison with other conventional topologies, namely the latched and the four-phase charge pumps, that shows the inherent advantage of the proposed solutions also in the range of input values higher than the MOS threshold voltage. 2-, 4-, and 6- stage versions of the conventional and proposed CPs have been fabricated in a 65-nm standard CMOS technology having a MOS threshold voltage equal to about 440 mV. Experimental results confirm the analytical predictions since the proposed topologies work at input voltage equal to 300 mV with a current load equal to$20~\mu \text{A}$and also confirm the advantages of the two proposed solutions in terms of settling time, output current drivability and output power density for voltages slightly higher (450 mV) than the MOS threshold voltage.

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology.

In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110μW thus confirming the advantages of the proposed approach.

The settling-time in single-pole operational transconductance amplifiers (OTAs) is analyzed including the effect of slew-rate limitations. A useful design equation is provided and extended to three-pole OTAs. A design procedure is carried out and validated through simulations.

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology.

In this paper we are going to analyze the settling-time in single-, two- and three-stage amplifiers with the intent of deriving approximate but useful design equations that include the effects of the zeros and of the slew-rate limitations. The analysis is mainly devoted to the definition of an approach for the design of three-stage CMOS operational transconductance amplifiers from settling-time specifications. A design example is carried out to validate the proposed approach.

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Post layout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74-μW power consumption for the high-speed design and a maximum frequency of 10 GHz with 53-μW power consumption for the minimum PDP design.

In this communication, we propose a new non-inverting class-AB CMOS output stage suitable for driving high-capacitive loads in three-stage amplifiers that make use of the Reversed Nested Miller technique for the frequency compensation. The output stage is verified through the design of a three-stage OTA suitable for driving a 500-pF capacitive load in a 65-nm CMOS process. The goodness of the proposed output stage is verified in the Cadence environment.

In this communication we propose a simple and well-defined approach for the design of fast settling amplifiers suitable for switched capacitors circuits. The design is based on a settling-time oriented compensation that makes the phase of the closed-loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The design and the simulation of a three-stage amplifier in a 65-nm CMOS process validate the proposed settling-time oriented approach.

This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and theoretically, thanks to a simple model of the propagation delay derived for both low-voltage topologies. In order to further demonstrate the advantages of the proposed topology, it has also been used to design a D flip-flop (DFF), where thanks to the feature to need just 1 clock differential pair; a further speed improvement is achieved over the conventional triple-tail topology. Indeed, by comparing a two-stage frequency divider designed using both the triple-tail DFF and the proposed folded DFF, a 54% improvement in the maximum operating frequency is found when using the proposed folded DFF.

The Silicon Photomultiplier (SiPM) is a promising kind of device able to detect single photons thus permitting the measurement of weak optical signals. The design of high-performance front-end electronics for the read-out, require an accurate model of the SiPM. In this paper we propose a new SiPM model implemented through the behavioral language Verilog-a and suitable for transistor-level circuit simulation. The model is based on a traditional electrical model and a statistical modeling to implement the SiPM noise characteristic in terms of dark-count and after-pulsing phenomena. We also provide a procedure for extracting the model parameters from measurements and validate both the extraction procedure and the Verilog-a model by comparing simulations to measurement results.

In this paper, a new class of pulsed latches is introduced and experimentally assessed in 65-nm CMOS. Its conditional push-pull pulsed latch topology is based on a push- pull final stage driven by two split paths with a conditional pulse generator. Two circuit implementations of the concept are discussed, with their main difference being in the pulse generator, which can be either shared (CSP3L) or not (CP3L). Measurements show that the proposed topology is very fast, as it outperforms the well-known transmission gate pulsed latch (TGPL) [1] by 1.5×-2×; hence the proposed pulsed latch has the highest performance ever reported. The proposed pulsed latch is also shown to significantly improve the energy efficiency compared to the state of the art. Indeed, a 2.3× improvement in ED3 product (energy × delay3) over TGPL was found for designs targeting minimum ED3. For designs targeting minimum ED, a 1.3× improvement was found in ED product. This comes at the cost of a 1.15×-1.35× cell area penalty, which translates into an overall area increase well below 1% in typical systems. Measurements on 256 replicas confirm that the above benefits are kept in the presence of variations. Accordingly, the proposed class of pulsed latches goes beyond the current state of the art and is well suited for VLSI systems that require both high performance and energy efficiency.

In this paper, a simple topology to reduce delay variations in domino logic gates is discussed. According to a previous analysis by the same authors, the feedback loop implemented by the keeper transistor and the output inverter gate is responsible for a delay variability increase, compared to static CMOS logic. The proposed strategy reduces the loop gain associated with this feedback loop, and hence its impact on delay variations. As a result, delay variations associated with the keeper insertion are lowered by approximately 50%, with no penalty in area, noise margin and nominal performance.

In this communication, an ultra-compact I-V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1-3% (always less than 6%) for the simple inverter case and within 4-8% (always less than 11%) in the case of stacked-transistor gates.

In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path. Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in the high-speed region.

In this paper, a comparison of representative Dual-Edge-Triggered flip-flop topologies is carried out in a 65-nm CMOS technology. The energy efficiency is analyzed together with other aspects, such as the area-delay tradeoff, leakage and clock-load, which are typically neglected in previous works. The investigation highlights the impact of effects that become dominant in nanometer technologies (e.g., local interconnects, leakage) and allows for identifying the most effective FFs belonging to the DET class, as well as to evaluate the suitability of DET topologies for real applications.

In this paper we show that, when dealing with transmission-gate based Master-Slave FFs, a reconsideration of the usual approach for high-speed design is worthwhile to improve energy-efficiency. By splitting such FFs in two separately optimized sections and then reconciling the results, the emerging design always outperforms that resulting from the employment of a classical procedure assuming FFs as a whole continuous path.

An accurate behavioral model for simulating Single-Photon Avalanche Diodes (SPADs) is introduced. The device operation is described using the Verilog-A description language. The derived model is able to emulate the static, the dynamic behavior and the main statistical effects of a SPAD, such as the turn-off probability, the dark-count and the after-pulsing phenomena. Spectre simulations reveal the validity of the approach.

The present paper addresses an improved and compact low-power high-speed buffer amplifier topology for large size liquid crystal display drivers. The proposed buffer achieves fast driving performance, draws a low quiescent current and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing and settling capabilities by realizing a dual-path push-pull operation of the output stage. No additional bias network is required to fix the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself without auxiliary power dissipation. Simulation results demonstrate that the suggested buffer can drive a 1000-pF column line capacitive load with a 5.8-V/μs slew-rate and a 0.75-μs settling time, while drawing only 3-μA quiescent current from a 3-V power supply.

In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff (e.g., leakage and the impact of layout and interconnects). Compared to previous papers on FFs comparison, the analysis involves a significantly wider range of FF classes and topologies. In particular, in this Part I, the comparison strategy, which includes the simulation setup, the energy-delay estimation methodology, and an overview of an optimum design strategy, together with the introduction of the analyzed FF classes and topologies, are reported.

In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed on the energy-delay-area domain, exploits the strategies and methodologies for FFs analysis and design reported in Part I. In particular, the analysis accounts for the impact of leakage and layout parasitics on the optimization of the circuits. The tradeoffs between leakage, area, clock load, delay, and other interesting properties are extensively discussed. The investigation permits to derive several considerations on each FF class and to identify the best topologies for a targeted application.

In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribution in clock domains, based on the proper choice of the clock slope. The suggested approach takes full advantage of the intrinsic features of DET Flip-Flops to achieve up to 50% energy-savings compared to traditional DET design approaches. The speed penalty, in terms of both FFs delay and local skew/jitter, is proven to be negligible through extensive simulations in a 65-nm CMOS technology.

In this paper the reversed nested Miller compensation (RNMC) approach is reviewed and its design equations are presented. After introducing two new compensation techniques, a coherent and comprehensive comparison of the available solutions is performed by means of a figure of merit expressing the trade-off among gain-bandwidth product, load capacitance and total transconductance, for equal values of phase margin. The proposed comparison outlines useful design guidelines for the optimization of the overall amplifier performance. Simulations proving the effectiveness of the suggested design methodology and analytical comparison are included, showing the substantial advantage of one of the proposed solutions.

This paper addresses a new compact low-power class-B buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by exploiting two current comparators embodied in the input stage, which sense the input signal transients to turn on the output stage transistors. A rail-to-rail stacked mirror differential amplifier is used to amplify the input signal difference and supply the bias voltages for the output stage. Simulation results show that the proposed buffer can drive a 1-nF column line load within 1.8-μs settling time under a full voltage swing, while drawing only 3.5-μA static current from a 3-V power supply.

This work addresses a new compact low-power highspeed output buffer amplifier topology for large-size LCD applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities by exploiting the push-pull output sections of two basic complementary-type input amplifiers to realize a dual-path push-pull operation of the output stage. An auxiliary bias network integrated in the input differential stage allows the quiescent conditions of the class-AB output stage to be inherently controlled without additional power dissipation. Post-layout results confirm that the proposed amplifier can drive a 1-nF capacitive load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current.

In this paper, the effect of process variations on delay is analyzed in depth for both static and dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay dependence on fan-in, fan-out, and sizing in sub-100-nm technologies. Simple but reasonably accurate models are derived to capture the basic dependences. The effect of process variations in transistor stacks is analytically modeled and analyzed in detail. The impact of both interdie and intradie variations is evaluated and discussed. Interestingly, the input capacitance of static and dynamic logic is shown to be rather insensitive to variations. The delay variability was also shown to be a weak function of the input rise/fall time and load. Analysis shows that domino logic circuits suffer from a doubled variability as compared to the static CMOS logic style. The positive feedback associated with the keeper transistor is shown to be responsible for the variability increase, which, in turn, limits the speed performance. This adds to the well-known speed degradation due to the current contention associated with the keeper transistor. Monte Carlo simulations on a 90-nm technology, including layout parasitics, are performed to validate the results.

In this paper, general metrics of the energy-delay (E-D) tradeoff in digital VLSI circuits are discussed. More specifically, the general class of metrics EiDjwith arbitrary exponents is adopted and evaluated for various commercial microprocessors. Results indicate that practical circuits are designed by minimizing a wider range of metrics compared to the ED or ED2metrics usually assumed in the literature. Hence, the general metrics EiDjdescribes the energy-delay tradeoff in a more realistic way. An interesting interpretation of the adopted metrics is provided to gain an insight into the relationship between energy and delay in energy-efficient designs. Various properties are also derived analytically by resorting to the logical effort method. Simulations on a 65-nm technology are performed to exemplify and validate the theoretical results.

This paper proposes and develops two simple efficient techniques for optimizing the closed-loop transient response of three-stage amplifiers for large capacitive load applications. The proposed approaches exploit a current comparator in the inner amplifier nodes to sense the input voltage transients and switch on an auxiliary driving device providing slew-rate enhancement and settling time improvement without extra static power dissipation. SPECTRE simulations are carried out on a three-stage amplifier adopting a recently proposed RNMC strategy with a voltage follower and two resistors. Simulation results confirm the effectiveness of both proposed techniques, showing a symmetrical step-response with a significant improvement in large-signal speed performance. Both discussed solutions are suitable for any particular three-stage amplifier topology and are also independent of the adopted compensation network.

This paper proposes and develops an original power-efficient reversed nested Miller compensation technique for low-power three-stage amplifiers driving large capacitive loads. The proposed approach exploits dual-active buffers in the compensation network, along with a feedforward gain stage providing enhanced speed performance. A well-defined design procedure for the compensation elements is also developed using the loop-gain phase margin as the main design parameter. To confirm the effectiveness of the proposed technique, SPECTRE simulations on a three-stage amplifier driving a 1-nF capacitive load are carried out adopting the model parameters of a standard 0.35 mum CMOS technology. Simulation results are finally found to be in excellent agreement with the theoretical analysis, showing a considerable improvement of the proposed strategy over other traditional solutions in terms of small-signal and large-signal performance.

In this paper, the energy consumption of resistance-inductance-capacitance (RLC) trees is analytically modeled. In particular, the results obtained by the same authors forRCtree circuits are generalized, allowing for a deep understanding of the impact of the inductance. The modeling approach proposed relies on the adoption of an equivalent second-orderRLCcircuit, whose energy consumption is evaluated in a closed form. These results are then extended toRLCcircuits with arbitrary order, deriving a simple and accurate model. The energy dependence on the input rise time is also analyzed in detail, identifying the ranges for which theRLCcircuit can be approximated to a simple capacitance or anRCcircuit. The model equations provide an insight into the dependence of the energy consumption on the circuit parameters. Indeed, the energy is explicitly expressed as a function of the resistances, capacitances and inductances of the original network. The energy model proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations, as the error is typically in the order of a few percentage points.

In this paper, MOS current mode logic (MCML) tapered buffers are discussed from a design point of view. Closed-form design equations that relate the overall speed performance and the power consumption of MCML tapered buffers are derived for nanometer CMOS technologies, i.e. by accounting for deep-sub-micron (DSM) effects from the beginning. The power-delay design space is then analytically explored, and design criteria are derived to properly size the number of stages and the current tapering factor under a speed/power constraint. The design criteria are simple enough to be used in pencil-and-paper calculations, as well as general and independent of the adopted technology. Hence, the proposed strategy provides the designer with an insight into the power-delay trade-off of MCML tapered buffers. Results are validated by means of simulations on a 90-nm CMOS technology.

In this paper, a simple and accurate model of the energy consumption in RLC trees with ramp inputs is proposed. The modeling approach is based on the reduction of the RLC tree network to a proper 2nd-order RLC equivalent circuit, according to the strategy proposed by the same authors in [1]. This approach leads to a closed-form expression of the energy consumption that allows for a deeper understanding of the contribution of the inductance, as well as of the effect of the input rise time. Thanks to its simplicity, the model is well suited for fast energy estimations. Extensive simulations show that the proposed approach is faster than SPICE simulations by four orders of magnitude. At the same time, the proposed approach provides results that are very close to SPICE simulations, with a typical error of 1.5%.

In this communication, we propose a Miller compensation technique for low voltage LDO regulators which makes use of a current amplifier. The analysis shows how to design the compensation network when no voltage buffer is placed between the LDO error amplifier and power device and suggests a low supply voltage circuit topology that allows to compensate with a reasonably low integrated capacitance, to avoid oscillations due to the complex-conjugate poles at high output currents and to obtain acceptable under/overshoots during fast transient load variations. The designed LDO regulator can work with a supply voltage down to 1.2 V with a drop-out voltage of 200 mV at maximum load current of 100 mA; the integrated compensation capacitance is 25 pF, the load capacitor being equal to 1 muF. Simulations in good agreement with the theoretical results are also shown.

In this paper, the mixed-topology Full Adder chains proposed in [1] are extensively analyzed versus technology. Analysis aims at exploring the power-delay design space in mixed-topology full adder chains, and evaluating the effect of technology scaling. The mixed-topology approach is also compared with the most representative single-topology circuits for technologies spanning five technology nodes (from 90 nm to 0.35 μm). All circuits are designed at the transistor and the physical level for different design targets, and results account for the layout parasitics. Results demonstrate that the mixed-topology approach is very competitive for every design target, and its advantage over single-topology circuits increases as down-scaling the technology. As a result, the mixed-topology approach is expected to be increasingly appealing when implementing Full Adder chains in down-scaled technologies.

In this paper, the design of high-fan-in CMOS multiplexers based on the heterogeneous-tree approach is discussed. In particular, a strategy to minimize the delay of multiplexers is developed that accounts for the interconnect parasitics from the beginning; thereby extending the previous results introduced in M. Lim (2000) which did not consider the effect of interconnects. The design criteria derived are very simple, and are shown to be strongly affected by interconnects, as one expects in current deep-submicron (DSM) VLSI circuits. It is also shown that neglecting parasitics in the multiplexer optimization can lead to speed degradation as high as 80%. The results are validated through post-layout simulations on a 90-nm CMOS process.

In this paper, the delay variability due to supply variations is investigated for the Transmission-Gate (TG) Full Adder topology, which is well known for its very low power consumption. The delay sensitivity with respect to supply variations is first analytically modeled. The resulting model is very simple, independent of the adopted technology and useful for better understanding the delay variations due to the supply voltage fluctuations. The delay sensitivity with respect to supply variations is also compared with that of traditional CMOS Full Adders, that are frequently adopted as a reference logic style. The results are validated by means of Spectre simulations with a 90-nm and a 0.18-μm technology.

A novel design-oriented approach for Miller compensation exploiting current buffer/amplifiers is described. The analysis enables a simple design procedure to be outlined, which is in turn applied to a two-stage CMOS OTA driving a large capacitive load. Assuming a 100-pF load, three example compensation networks were designed using alternatively a compensation capacitor as low as 1.3 pF, 0.6 pF and 250 fF. Simulations in very good agreement with theoretical results are also given.

We propose a representation and a related methodology for evaluating the exact input and output resistances of feedback amplifiers. The approach is based on the generalization of the Rosenstark theorem. Indeed, it requires the computation of two resistances (direct and asymptotic) each one evaluated in one of the two ideal and extreme conditions of the return ratio (zero or infinity). Due to these characteristics, the representation allows one to understand what happens to a feedback amplifier resistance in the case of absence of feedback or in the ideal case of infinite feedback.

In this paper, the delay uncertainty due to supply variations is investigated for two important full adder topologies. In particular, it is developed an analytical model of the delay sensitivity to supply variations for the static mirror adder and the dynamic dual-rail domino adder. The model is general and very simple, and allows for identifying the main parameters which define the delay uncertainty due to supply variations, as well as deriving design considerations. In particular, the importance of the input rise/fall time variations is clarified, and the effect of the supply voltage reduction and technology scaling is discussed. Results are validated through SPICE simulations with a 0.18-mum and a 0.35-mum technology

In this paper, analytical models of the static and dynamic behavior of MOS current-mode logic (MCML) with a resistive load are discussed. These models account for deep-submicron (DSM) effects which affect the operation of this CMOS logic style in the nanometer regime. In particular, a noise margin model is derived by resorting to the alpha-power law, and comparison with the long-channel expression allows for clearly understanding the impact of DSM effects. The dynamic behavior is also analyzed by accurately modeling the resistive load, i.e. accounting for its capacitive parasitics, which are shown to give an important contribution in low-power designs. Analytical results and considerations are validated by means of Spectre simulations on a 90-nm CMOS technology

In this paper, the modeling of the output transition time in deep-submicron (DSM) CMOS gates is discussed. In particular, the analysis starts from a previously proposed analytical model valid only for ramp inputs (Maurine et al., 2002 and Auvergne et al., 2000). This model is then improved by introducing two semi-empirical coefficients which have to be tuned by means of two SPICE simulations. Since an exponential input is more and more frequent in current DSM CMOS technologies, the model is extended to this kind of input waveform. Results are validated with simulations on a 0.18-mum CMOS technology. The output transition time model is found to be in good agreement with SPICE simulations, with an average error of only 5%

A novel frequency compensation technique for three-stage amplifiers is introduced. Compared to the traditional reversed nested Miller compensation strategy, the proposed one exploits two active stages already included in the amplifier topology, thus no extra circuitry for its implementation is needed. The technique allows to remove the right-half-plane zero and generates a left-half-plane zero, improving the phase margin. Design equations using the phase margin as design parameter are carried out. The proposed technique is used to design, using a standard CMOS 0.35-mum technology, a 2-V three-stage amplifier driving a 500-pF load. The amplifier dissipates 0.24 mW at DC and achieves a 1.75-MHz gain-bandwidth product

A simple technique to evaluate the linearity performance of a tunnel diode oscillator is presented. The approach is based on the phasor method and avoids redundant computations and/or iterations required by traditionally adopted mathematical tools. Equations found are simply derived, extend our knowledge on harmonics generation and are particularly useful for the designer. A design example is provided and simulations are found in good agreement with expected results

In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on the supply voltage fluctuations, which are a major contribution to the delay uncertainty, which in turn limits the speed performance of current VLSI circuits. Analytical models of the delay sensitivity with respect to supply variations are derived by following a simplified circuit analysis, and the resulting expressions are simple enough to afford a deeper insight into the impact of supply voltage variations on each topology. The models are shown to be sufficiently accurate through simulations with CMOS technologies having a minimum feature size ranging from 90 nm to 0.35 mum. Several interesting properties and design considerations are derived from these models, and the effect of the supply voltage scaling, technology scaling, transistor sizing, and input transition time is discussed. Strategies to evaluate the delay sensitivity since the early design phases (e.g., from ring oscillator measurements) are also introduced. As a fundamental result, it is shown that the delay sensitivity to supply variations will increase in the next technology nodes, thus, it is expected that controlling the supply variations will be an increasingly important issue in the design of the next generation VLSI circuits. The proposed methodology is also analyzed in the case of more general digital circuits, and is used to estimate the impact of the inter-die threshold voltage variations on the delay of the considered full adder topologies

In this paper, resistance-capacitance (RC) tree networks are modeled in terms of their energy consumption associated with an input transition. This work significantly extends the results that the same authors previously obtained in the specific case of ladder networks with only ramp signals. The proposed approach to model the energy consumption is based on a single-pole approximation, in which an equivalent time constant is analytically derived from an exact analysis for very slow and very fast input transitions. The model is then extended to arbitrary values of the input rise time by exploiting some intrinsic properties of RC tree networks. The approach is completely analytical and leads to closed-form results. Analytical results are explicitly derived for different inputs, such as the ramp and the exponential waveforms which are usually encountered in current VLSI circuits, as well as the saturated sine input. Due to its simplicity, the proposed energy expression is suitable for pencil-and-paper evaluation and allows for an intuitive understanding of the network dissipation. The energy expression proposed is shown to be accurate enough for modeling purposes through comparison with SPICE simulations.

In this paper, the energy consumption of RC ladder networks, which can represent chains of transmission gate or long wire interconnections, is modeled. Their energy dependence on the input rise time is analyzed by assuming a ramp input waveform. Since the analysis can be carried out in a straightforward manner only for very simple RC ladder networks, the exact analysis is first limited to asymptotic values of the input rise time T (i.e., for T/spl rarr/0 and T/spl rarr//spl infin/). Successively, the energy expression is extended to arbitrary values of the input rise time by introducing a suitable equivalent first-order RC circuit, whose resistance and capacitance are simply related to the resistances and capacitances of the original network. The energy expression found is useful for pencil-and-paper evaluation and affords an intuitive understanding of the network dissipation, since each term has an evident physical meaning. By comparison with SPICE simulations, the energy expression proposed is showed to be accurate enough for modeling purposes.

In this paper a low power strategy for a TFT controller is described. The design is based on a general controller for high resolutions graphic display data. The main improvements introduced concerns not only an effective power reduction of about 65.42%, compared with the original module, but also the new feature that allows one to choose among six different functional configurations. The new TFT controller works also with the new display generation such as organic LED (OLED) type, in this case we introduce the possibility to power down the backlighting neon. Measures are made with design compiler (Synopsys) to compute the TFT controller power consumption and the total cell area before and after our modifications.

This paper presents a general architecture for an analog-to-digital (A/D) fuzzy converter which performs the A/D conversion and the fuzzification operation on the same functional block, through a programmable membership function. The solution uses as main blocks an A/D converter, a comparator, and some logic inverters and switches. It is characterized by good flexibility and programmability and, compared to conventional approaches, allows a significant amount of silicon area to be saved. The architecture proposed does not depend on the specific A/D converter adopted. However, low-voltage operation and reduced power dissipation as well as full compatibility with digital technologies can be achieved through the use of current-mode design techniques. A CMOS implementation is then proposed and nonidealities, limiting the resolution, are analytically evaluated in detail. Simulations based on a 0.35-/spl mu/m standard technology, which are in excellent agreement with the theoretical results, are also given.

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on two classes of circuits, the former with minimum transistor size to minimize power consumption, the latter with optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.35-/spl mu/m process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive. In contrast, the most interesting implementations in terms of trade off between power and delay are the traditional CMOS and mirror topologies. Moreover, the dual-rail domino and the CPL allow the best speed performance.

A simple procedure to evaluate the energy consumption of adiabatic gate circuits is proposed and validated. The proposed strategy is based on a linearization of the circuit and simplifying the analytical result obtained on the equivalent network. The approach leads to simple relationships which can be used for a pencil-and-paper evaluation or implemented on software. The accuracy of the results is validated by means of Spice simulations on an adiabatic full adder designed with a 0.8 /spl mu/m technology.

In this paper a simple and accurate model to evaluate the energy consumption of the digital adiabatic circuits is proposed. It is based on a linearization of the circuit, which leads to an RC mesh equivalent circuit. The obtained expression of the energy consumption of a generic adiabatic gate is very simple, thus it can be used for pencil-and-paper calculations. The predicted values were compared to Spice results using a 0.8 /spl mu/m CMOS technology. The average error is below 3.5%, and for practical switching frequencies the maximum error is always lower than 8%. Therefore, the proposed model can be also used to implement an accurate and efficient power simulator tool.

This paper presents modeling and optimized design of Current Mode Logic (CML) MUX. Propagation delay models with few terms are presented. The most accurate model has errors lower than 2%. By using the proposed models a design optimization is proposed. In particular, the bias currents which gives the minimum propagation delay are found. Moreover, it is demonstrated that at the cost of a 10% increase in propagation delay a 40% reduction in the power dissipation can be achieved. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 GHz and 20 GHz, respectively.

A new Switched Capacitor Membership Function circuit, which is based on an offset insensitive SC amplifier and presents triangular-shape transcharacteristics, is proposed. Thanks to the SC approach a good precision, which is independent of process tolerances, is achieved. The circuit was realised in a 1.2-/spl mu/m standard CMOS technology and both simulations and experimental data were carried out. Good agreement is shown between expected and measured values.

In this paper simple and accurate models for the propagation delay of both current mode logic (CML) and emitter-coupled logic (ECL) gates are proposed. The models start from the small signal model properly evaluated. This makes it possible to represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need few Spice simulations to properly evaluate the model parameters. In order to validate the models, a comparison using both a traditional and a high-speed bipolar process was carried out under many bias conditions and output loads. Simple models have typical errors of around 20%. Accurate models have typical errors as low as 2% and 5% for CML and ECL, respectively, while the worst case error is as low as 5% and 8% for CML and ECL, respectively.

Accurate and simple models of CML propagation delay are given. The approach used is new. The propagation delay is represented with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The most accurate model has a typical and worst case errors as low as 2% and 5%, respectively.

New and simple CMOS mixer powered with 1.5 V is presented. It works with a 200 MHz clock, and has a -7-dB IP/sub 3/. Moreover, it elaborates signals up to 150 mV with 1-dB compression point. The particular topology makes it useful for an integration in fully digital ICs.

A novel CMOS CCII is presented which provides a voltage transfer error better than /spl plusmn/0.1 dB with resistances greater than 25 /spl Omega/. Moreover, the resistance at terminal X is as low as 0.3 /spl Omega/. Thanks to its simple topology, the circuit is particularly suitable as input stage of current feedback operational amplifiers and current operational amplifiers.

In this paper we develop a dynamic model for the 4 stage Dickson voltage multiplier. Starting from the model proposed, optimized design can be performed. The circuit discussed is commonly used in power ICs or memory to allow the switching on of an MOS device. The model proposed is validated both by measurement and SPICE simulation.>

A high-accuracy high-speed current comparator is presented which has well-controlled input resistance and bias currents. Moreover, compared to previous high-speed solutions, it has an accuracy five times better with a lower power consumption.>

This paper presents an optimized design for the Wilson and improved Wilson MOS current mirrors. The paper includes a detailed analysis of the high-frequency behaviour of the Wilson and improved Wilson MOS current mirrors, which shows a current transfer function with two poles and one zero. The optimized designs leads to a response which is better than that of the simple current mirror. The proposed design is verified with Spice simulation of the current mirror in a CMOS 2-/spl mu/m technology.>