Alan Peisheng Su

dblp:60/7450 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 44% Parallel and multicore computing · 44% Interconnection networks and networks-on-chip · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
multicore design
0.112009
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core · DAC 2009
Parallel and multicore computing › parallel computing › parallel program analysis › concurrency bug detection
race detection
0.112009
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core · DAC 2009
Interconnection networks and networks-on-chip
ring network
0.012009
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core · DAC 2009

Methods — techniques the papers use, named apart from their topics

page-based monitoring cache · 0.1non-uniform debug architecture · 0.1
YearPublicationVenuePosition
2009 NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core
abstract
Traditional debug methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with software debugging tools. Most traditional debugging approaches rely on globally synchronized signals, but these pose problems in terms of scalability. The first contribution of this paper is to propose a novel nonuniform debug architecture (NUDA) based on a ring interconnection schema. Our approach makes debugging both feasible and scalable for many-core processing scenarios. The key idea is to distribute the debugging support structures across a set of hierarchical clusters while avoiding address overlap. This allows the address space to be monitored using non-uniform protocols. Our second contribution is a non-intrusive approach to race detection supported by the NUDA. A non-uniform page-based monitoring cache in each NUDA node is used to watch the access footprints. The union of all the caches can serve as a race detection probe. Using the proposed approach, we show that parallel race bugs can be precisely captured, and that most false-positive alerts can be efficiently eliminated at an average slow-down cost of only 1.4%~3.6%. The net hardware cost is relatively low, so that the NUDA can readily scale increasingly complex many-core systems.
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan Peisheng Su
DAC4