The flight time of uncrewed autonomous vehicles (UAVs) is constrained by its battery capacity, restricting its application in long-duration missions. To address this challenge, we propose eFlight, a hybrid scheme that uses a reinforcement-learning heuristic to augment A* for path finding. eFlight reduces both node expansions and computation time while finding energy-efficient paths in obstacle-dense 3D airspace. We compare eFlight with conventional path-planning algorithms for point-to-point flights on areas of various dimensions and with various obstacle densities. The results show that eFlight achieves a dual advantage: finding low-energy paths with short computation times. In high-density obstacle environment, eFlight identifies the lowest energy consumption path in 89.5% of the trials. Compared to the baseline scheme, eFlight reduces computation time by 90.6% ± 26.6% and energy by 7.13% ± 9.96%.

We propose a deadline-aware flow scheduling scheme, called Preemptive Efficient Queuing (PEQ), which takes both the deadlines and sizes of the flows into account for efficient flow scheduling of flows in a data-center network in this paper. PEQ benefits from evaluating the deadlines and flow sizes of flows to improve application throughput. Our results show that PEQ outperforms the state-of-the-art deadline-aware transport schemes in terms of the application throughput and average flow completion time, under traffic with different deadline distributions. Results also show that PEQ yields a near-optimal application throughput in cases where short flows have long deadlines and long flows have strict deadlines. In other words, PEQ attains higher performance than the counterpart schemes on traffic with broader distribution of deadlines and flow sizes.

We propose a configuration scheme for a load-balancing Clos-network (LBC) packet switch that has split central modules and buffers in between the split modules. Our split-central-buffered LBC switch is cell-based. The switch has four stages, namely input, central-input, central-output, and output stages. The proposed configuration scheme uses a pre-determined and periodic interconnection pattern in the input and split central modules to load-balance and route traffic. The LBC switch has low configuration complexity. The operation of the switch includes a mechanism applied at input and split-central modules to forward cells in sequence. The switch achieves 100% throughput under uniform and nonuniform admissible traffic with independent and identical distributions (i.i.d.). The switch uses no speedup nor memory expansion. We demonstrate the properties of the switch through traffic and timing analysis.

As transmission speeds increase faster than processing speeds, the packet processing time (PPT) of a host is becoming more significant in the measurement of different network parameters in which packet processing by the host is involved. The PPT of a host is the time elapsed between the arrival of a packet at the data-link layer and the time the packet is processed at the application layer (RFCs 2679 and 2681). To measure the PPT of a host, stamping the times when these two events occur is needed. However, time stamping at the data-link layer may require placing a specialized packet-capture card and the host under test in the same local network. This makes it complex to measure the PPT of remote end hosts. In this paper, we propose a scheme to measure the PPT of an end host connected over a single- or multiple-hop path and without requiring time stamping at the data-link layer. The proposed scheme is based on measuring the capacity of the link connected to the host under test. The scheme was tested on an experimental testbed and in the Internet, over a U.S. inter-state path and an international path between Taiwan and the U.S. We show that the proposed scheme consistently measures PPT of a host.

In this paper we propose a three-stage space-space-memory (SSM) Clos-network switch that uses crosspoint buffers in the third-stage modules to eliminate the need for performing multiple iterations in for port matching. We show that the proposed switch not only reduces the configuration complexity of space-space-space (S3) switches but also improves switching performance and relaxes configuration timing. We demonstrate these advantages by comparing the performance of the proposed switch using the weighted module-first no-port (WFM-NP) matching scheme to that of a S3switch using the original scheduling scheme (with port matching). For higher utilization of the SSM switch, we propose the weighted central-module-link matching (WCMM) scheme. The WCMM scheme rescinds multiple iterations for module matching and yet, it achieves higher performance than the WFM-NP scheme. The advantages of the SSM switch are achieved without memory speedup. The memory addition is a small cost to trade for complexity reduction and performance improvement.

Virtual output queues (VOQs) is widely used by input-queued (IQ) switches to eliminate the head-of-line (HOL) blocking phenomenon that limits matching and switching performance. It has been shown that IQ switches can provide 100% throughput under admissible traffic when using maximum-weight matching schemes or iterative maximal-weight matching schemes with a speedup of two or more. These different approaches require either a high computation complexity or large resolution times for high-speed switches. Therefore, there is a need for low-complexity and fast matching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions, without recurring to speedup nor multiple iterations. We proposed earlier weightless matching schemes based on the captured-frame concept for IQ switches to provide high throughput under uniform and nonuniform traffic patterns, when using a single iteration and no speedup. In this paper, we proposed to use the capture-frame concept in weighted matching schemes and show that performance improvement can be achieved. We apply this concept to the longest-queue first (LQF) selection to create the unlimited LQF (uFLQF) schemes. We show via simulation that uFLQF achieves high throughput under uniform and nonuniform traffic patterns with a single iteration.

Clos-network switches were proposed as a scalable architecture for the implementation of large-capacity circuit switches. In packet switching, the three-stage Clos-network architecture uses small switches as modules to assemble a switch with large number of ports or aggregated ports with high data rates. Current schemes for configuration of input-queued three- stage Clos-network (IQC) switches involve port matching and path routing assignment, in that order. The implementation of a scheduler capable of matching thousands of ports in large-size switches is complex because of the large port count. To decrease the scheduler complexity for such switches (e.g., 1024 ports or more), we propose a configuration scheme for IQC switches that hierarchizes the matching process. In a practical scenario our scheme performs routing first and port matching thereafter. This approach applies the reduction concept of Clos networks to the matching process. The application of this approach results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a 3-stage switch. We show that the switching performance of the proposed approach using weight- based and weightless selection schemes is high under uniform and nonuniform traffic.

Virtual output queues (VOQs) are widely used by input-queued (IQ) switches to eliminate the head-of-line (HOL) blocking phenomena, which limits switching performance. An effective matching scheme must provide high throughput under several admissible traffic patterns and keep implementation complexity low. A variety of matching schemes for IQ switches that deliver high throughput under uniform traffic have been proposed. However, there is a need of matching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions. In this paper, we introduce the captured frame-size concept for matching schemes in IQ switches. We use the captured-frame eligibility concept in a round-robin based scheme, uFORM, and in a random-base scheme, uFPIM, to improve switching performance under nonuniform traffic patterns. The uFPIM scheme is based in the parallel iterative matching (PIM) scheme and shows the throughput improvement achieved with the captured frame concept. The uFORM scheme provides high performance under nonuniform traffic while keeping the high performance that round-robin schemes are known to have under uniform traffic.

The use of virtual output queues (VOQ) in input-queued (IQ) switches can eliminate the head-of-line (HOL) blocking phenomenon, which limits switching performance. An effective matching scheme for IQ switches with VOQ must provide high throughput under admissible traffic patterns while keeping the implementation feasible. This paper proposes a matching scheme for IQ switches that provides high throughput under uniform and a nonuniform traffic pattern, called unbalanced. The proposed matching scheme, FORM, is primarily based on round-robin selection and the captured-frame concept. We show via simulation that this scheme delivers over 99% throughput under unbalanced traffic and retains the high performance under uniform traffic that round-robin matching schemes are known to offer.