Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Seongyoon Kim

dblp:60/9801 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
2since 2021 · last 2023
0000-0001-7326-5681ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 2 since 2021Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Trustworthy machine learning · 67% Deep learning architectures and training · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Trustworthy machine learning › robustness
dataset bias mitigation
0.712023
Mitigating Dataset Bias by Using Per-Sample Gradient · ICLR 2023
Machine learning › Trustworthy machine learning
fairness
0.712023
Mitigating Dataset Bias by Using Per-Sample Gradient · ICLR 2023
Machine learning › Deep learning architectures and training › training optimization
gradient-based training
0.712023
Mitigating Dataset Bias by Using Per-Sample Gradient · ICLR 2023

Methods — techniques the papers use, named apart from their topics

reweighting · 0.7per-sample gradient · 0.7
YearPublicationVenuePosition
2023 Mitigating Dataset Bias by Using Per-Sample Gradient
Sumyeong Ahn, Seongyoon Kim, Se-Young Yun
ICLR2
2022 Recurrent neural network-induced Gaussian process
Seongyoon Kim
Neurocomputing2
2009 An SoC Integrating an H.264 Encoder with an ISP
abstract
The SoC presented in this paper integrates an H.264 encoder with an ISP (Image Signal Processor). It is currently implemented in an FPGA and processes an HD-size (1280 × 720) image at the speed of 15 fps with the operating clock frequency of 50 MHz. In the presented demo system, a Bayer input from a CMOS image is given to the FPGA and the output stream is transmitted through an USB transceiver to a PC that decodes and displays the H.264 stream.
Eung Sup Kim, Seongyoon Kim, Gyoung-Hwan Hyun, Jin-Su Jung, Chae-Eun Rhee, Yongseok Jin
ISCAS2