EDBT 2026 Demo / reviewers in the wild / expert
Alyosha C. Molnar
dblp:61/10277 · also Alyosha Christopher Molnar
· DBLP profile ↗
17ranked-venue papers
0as first author
12since 2021 · last 2025
0000-0001-7674-1874ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 12 · 10 since 2021Graphics, computer vision, multimedia, augmented reality and games · 4 · 1 since 2021Artificial intelligence and machine learning · 2 · 1 since 2021Computer networks · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | A 43 µm × 269 µm, Light-Tolerant and Power-Adaptive Forward-Bulk Optoelectrical Microsystem for Tetherless Neural RecordingabstractA sub-nanoliter, light-tolerant (780 µW/mm2), and power-adaptive forward-bulk optoelectronic microsystem for tetherless neural recording is presented. The CMOS bulk is used as a power harvester to utilize photogenerated carriers and a lower transistor threshold voltage for low power design (~0.3 µA at ~0.32 V). Increasing optical power boosts the system bandwidth to 14 kHz and the sampling frequency to 18.2 kHz, while maintaining the integrated input-referred noise (~10 µVRMS) stable, with an NEF of 2.34. Yumin Zheng, Shahaboddin Ghajari, Sanaz Sadeghi, Alejandro J. Cortese, Paul L. McEuen, Alyosha C. Molnar, Sunwoo Lee 0002 |
ISCAS | 7 |
| 2025 | Scaling Co-Packaged Optical Interconnects Using Hybrid 2.5D/3D IntegrationabstractTightly integrated optical interconnects can provide high-bandwidth, energy-efficient inter-node communication. We describe a novel system which uses hybrid 2.5D/3D integration to compose a state-of-the-art FPGA compute chiplet, three electrical interface chiplets, and three photonic interface chiplets. We use register-transfer-, gate-, transistor-, and device-level simulations to demonstrate the potential for this system to achieve 96Tb/s of bi-directional bandwidth, and we experimentally demonstrate key components including a complete opto-electrical channel. Our results provide a strong case for hybrid 2.5D/3D integration as the key enabler for scaling co-packaged optical interconnects. Austin Rovinski, Yanghui Ou, Christine Ou, Devesh Khilwani, Yuyang Wang 0003, Songli Wang, Sunwoo Lee 0002, Keren Bergman, Alyosha C. Molnar, Christopher Batten |
ISCAS | 9 |
| 2025 | Synthetic Diversity for Artifact Suppression and Simultaneous Multi-Band Down-Conversion in Widely-Tunable ReceiversabstractThis paper presents a novel system architecture to suppress in-band artifacts (IBAs) generated from out-of-band (OOB) interferers, including reciprocal mixing by the local oscillator’s (LO) spurs and phase noise (PN), third-order intermodulation (IM3) artifacts, and harmonic down-conversion (HDC) artifacts. Theory and design procedure are explained, and measurement results from a prototype taped out in 45 nm RF SOI process are presented. The receiver was designed for the frequency range of 1.2 GHz–2.4 GHz and achieved a noise figure (NF) of 3.1 dB–6.2 dB, blocker −1 dB compression point (B1dB) of −10.3 dBm, and OOB third-order input-referred intercept point (IIP3) of 9.3 dBm on average, before artifact suppression. Measurements were performed on 16-quadrature amplitude modulated (16QAM) signals with modulated and unmodulated OOB interferers to show artifact suppression for various kinds of IBA. For each IBA, artifact suppression performance was assessed across frequency and interferer power. Interference tolerance improvement of up to 38 dB was achieved. Additionally, reconstruction of the artifacts for the cases of spur and HDC was demonstrated, showing simultaneous recovery of two signals, providing a form of carrier aggregation. Sanaz Sadeghi, Jamie C. Ye, Bernd-Peter Paris, Alyosha C. Molnar |
IEEE Trans. Circuits Syst. I Regul. Pap. | 4 |
| 2024 | 3D-Integrated, Low Power, High Bandwidth Density Opto-Electronic TransceiverabstractWe demonstrate a dense, highly parallel, and scalable multi-channel transceiver array for photonic chip-to-chip links. A CMOS electronic chip is flip-chipped onto a silicon photonic chip with 25 μm-pitch bumps to enable 0.8 Tbps data transmission through a single fiber utilizing a comb laser at a record bandwidth density of 5.3 Tbps/mm2. The unit transmitter and receiver cells inside the 80 channel-array incorporate high speed circuitry to drive, read from, and tune the photonic elements, while only occupying 25 μm × 75 μm each. Devesh Khilwani, Sunwoo Lee 0002, Christine Ou, Stuart Daudlin, Anthony Rizzo, Songli Wang, Michael Cullen, Keren Bergman, Alyosha C. Molnar |
ISCAS | 9 |
| 2023 | Redox-Enabled Microscale Opto-Electronically Transduced Electrodes (ReMOTEs)abstractWe present the elements of a pH-measuring autonomous microsystem, a Redox-Enabled Microscale Opto-Electronically Transduced Electrode (ReMOTE). The ReMOTE contains two electrodes of different materials, where the nearby$\mathbf{pH}$dictates the voltage between the two electrodes. The ReMOTE is a tetherless, all-optical microsystem which is powered and is transmitting its data optically. The ReMOTE is designed in a 180 nm CMOS SOI process, occupies merely$\mathbf{417}\ \mu \mathbf{m}\times \mathbf{48}\ \mu \mathbf{m}$, and it only consumes$\mathbf{2}\ \mu\mathbf{W}$. For the functional verification, we have conducted pH measurements using a thin film titanium nitride working electrode and a Ag/AgCl reference electrode, of which the voltage per pH sensitivity was 42.53 mV/pH. Shahaboddin Ghajari, Sunwoo Lee 0002, Samantha L. Norris, Paul L. McEuen, Alyosha C. Molnar |
ISCAS | 5 |
| 2023 | Analog-Domain Self-Interference Cancellation for Practical Multi-Tap Full-Duplex System: Theory, Modeling, and AlgorithmabstractPractical, in-band, full-duplex (IBFD) systems typically require more than 100 dB of self-interference cancellation (SIC). Digital processing alone is insufficient for achieving this target, which drives us towards supplementary analog mitigation techniques. We propose an analog-domain, self-interference cancellation circuit to enable pass-band, analog SIC in an IBFD system. Analog SIC is limited by several hardware constraints and design choices, including finite tap-delay resolution, non-negative tap constraints, and bit precision quantization. We characterize the performance impact of each of these limitations as a function of signal bandwidth, carrier frequency, bit precision, and other system design parameters. We further characterize the achievable system performance under all of these limitations combined. We simulate several realistic examples to illustrate the relationship between the achievable self-mitigation performance and various system design choices. We implement a simple constrained optimization algorithm informed by these results to optimize the tap-delay weights of the analog circuit under these system constraints. We simulate the achievable mitigation performance and demonstrate as much as 45 dB of analog-domain, self-interference mitigation of a wide-band signal with realistic system configurations. Carl W. Morgenstern, Yu Rong 0002, Andrew Herschfelt, Alyosha C. Molnar, Alyssa B. Apsel, David G. Landon, Daniel W. Bliss |
IEEE J. Sel. Areas Commun. | 4 |
| 2022 | First Arrival Differential LiDARabstractSingle-photon avalanche diode (SPAD) based LiDAR is becoming the de-facto choice for 3D imaging in many emerging applications. However, they suffer from three significant limitations: (a) the additional time-of-arrival dimension results in a data throughput bottleneck, (b) limited spatial resolution due to either low fill-factor (flash LiDAR) or scanning time (scanning-based LiDAR), and (c) coarse depth resolution due to quantization of photon timing by existing SPAD timing circuitries. In this paper, we present a novel, in-pixel computing architecture that we term first arrival differential (FAD) LiDAR, where instead of recording quantized time-of-arrival information at individual pixels, we record a temporal differential measurement between pairs of pixels. FAD captures relative order of photon arrivals at the two pixels (within a cycle or laser period) and creates a one-to-one mapping between this differential measurement and depth differences between the two pixels. We perform detailed system analysis and characterization using Monte Carlo simulation, and experimental emulation using a scanning-based single-photon avalanche diode. FAD pixels can result in a 10–100x reduction in per-pixel data throughput compared to TDC-based pixels. Under the same bandwidth constraints, FAD-LiDAR achieves better depth resolution and/or range than several state-of-the-art TDC-based LiDAR baselines. Mel J. White, Akshat Dave, Shahaboddin Ghajari, Ankit Raghuram, Alyosha C. Molnar, Ashok Veeraraghavan |
ICCP | 6 |
| 2022 | Mapping Unknown Environments With Instrumented Honey BeesabstractRecent innovations in miniature sensors are driving a shift from robotic to bio-hybrid systems for exploration of unstructured environments. The ubiquity of honey bees in modern agriculture and ecology along with their superior agility, olfactory sense, and collective foraging skills make them a promising complement to traditional robots. This paper explores the potential of such systems based on a custom honey bee foraging simulator and models of state-of-the art miniature flight recorders which can measure solar heading at regular time intervals, as well as exploratory data collected from the sensor mounted on an autonomous quadrotor. The size and functionality of the sensor is heavily influenced by its memory footprint, therefore, we investigate the impact of sensor sampling time on map accuracy. Our results indicate that a sampling rate down to 5Hz can be used to sense obstacle locations in a 5-acre field with an accuracy corresponding to 70% of the obstacle radius, and within 4% of its true area. This technique shows promise for using instrumented honey bees to map and monitor unstructured environments which are difficult or costly for robots to robustly navigate, monitor, and map. Haron Abdel-Raziq, Daniel Palmer, Alyosha C. Molnar, Kirstin Petersen |
ICRA | 3 |
| 2022 | LO Synchronization Scheme via Full-Duplex Transceiver for Distributed Beamforming in Wireless Ad hoc NetworksabstractIn this paper, we demonstrate a prototype system for path independent local oscillator (LO) synchronization of a distributed beamformer in wireless ad hoc networks. The system contains a low power full duplex (FD) transceiver IC, a RF phase interpolator IC, and a CDMA encoder/decoder to realize a conjugate loop and synchronize the LO’s of two RF nodes. Both ICs were fabricated in 180nm CMOS technology. The FD transceiver IC consumes 69mW at 700MHz and the RF phase interpolator IC consumes 75mW at 1.4GHz. Using the low power ICs, we demonstrate a simple, lightweight, and robust methodology to synchronize two LO’s with an average phase precision of 2.1° and 94% maximum beamforming gain using RF only transmissions via a single antenna per node. Olalekan Afuye, Shimin Huang, Ken Ho, Alyosha C. Molnar, Alyssa B. Apsel |
ISCAS | 4 |
| 2022 | Widely-Tunable RF Receiver Employing Synthetic Diversity for Interference MitigationabstractThis paper presents a novel technique for suppression of in-band artifacts from out-of-band (OOB) interference in widely tunable RF receivers. The technique employs a multi-tap inductor-capacitor network (LCN) to generate diversity in gain and phase between taps across the targeted frequency range. Using this network to feed a bank of identical receivers sharing a single local oscillator (LO) allows multiple kinds of interferer artifact to be suppressed. Here we considered spur-induced and phase noise-induced artifacts. In each case, the resulting artifacts are linearly separable from signal when the outputs of the sub-receivers are recombined. AC and transient simulations were first performed to show feasibility of the proposed approach. A prototype was implemented in 45nm CMOS which confirmed the validity of the synthetic diversity (SD) approach for suppressing interferer artifacts, showing a maximum lowering in EVM and BER of 38% and 60% respectively. Sanaz Sadeghi, Sweta Soni, Alyosha C. Molnar |
ISCAS | 3 |
| 2022 | A Differential SPAD Array Architecture in 0.18 μm CMOS for HDR ImagingabstractWe propose a scalable architecture for a differential single-photon avalanche diode (D-SPAD) array which generates measurements based on differential time-of-arrival in lieu of absolute time-of-arrival. This design addresses the throughput bottleneck in conventional sensors that record time-of-arrival statistics (such as histograms or raw arrival-time data) directly. In addition, this design also mitigates saturation at the pixel level and at the counter, making it an ideal candidate for use when the scene being imaged covers a high dynamic range (HDR). The differential nature of the data also obviates the need for large digital circuitry such as high bit depth counters or time to digital converters (TDCs). A prototype test structure of 16 pixels was fabricated in 0.18 $\mu$m CMOS, and we show images reconstructed from this chip that illustrate its capabilities. Mel J. White, Shahaboddin Ghajari, Akshat Dave, Ashok Veeraraghavan, Alyosha C. Molnar |
ISCAS | 6 |
| 2021 | Impedance Transparency and Performance Metrics of HBT-Based N-Path Mixers for mmWave ApplicationsabstractMOS N-path mixer-first receivers are capable of providing instantly-reconfigurable RF impedance and bandwidth while achieving moderate noise figure (NF) and high linearity, but their frequency tuning range is limited by both LO (local oscillator) generation and the RF port input capacitance. State-of-the-art mm-wave MOS N-path receivers often compromise performance to cover the mm-wave range, but this paper presents the theory and design considerations for a new topology of N-path mixer which makes use of high fTHBTs and breaks this trade-off between performance and tuning range. Here, we borrow from a previously derived LTI model for MOS-based N-path mixers to derive an analogous model for the HBT-based counterpart which provides a meaningful comparison between the performance of the two topologies. We show that the HBT-based implementation is capable of operation beyond the frequency limits of MOS-based implementations while maintaining comparable NF and linearity without consuming exorbitant power. Measurements done on a proof-of-concept chip in GlobalFoundries BiCMOS8HP are consistent with our models and simulations. By organizing process parameters and user-selected design variables into dimensionless ratios, we provide expressions for key performance metrics which enable the designer to make informed decisions about trade-offs and optimizations for both LO generation and the mixer core. Robin Ying, Alyosha C. Molnar |
IEEE Trans. Circuits Syst. I Regul. Pap. | 2 |
| 2016 | ASP Vision: Optically Computing the First Layer of Convolutional Neural Networks Using Angle Sensitive PixelsabstractDeep learning using convolutional neural networks (CNNs) is quickly becoming the state-of-the-art for challenging computer vision applications. However, deep learning's power consumption and bandwidth requirements currently limit its application in embedded and mobile systems with tight energy budgets. In this paper, we explore the energy savings of optically computing the first layer of CNNs. To do so, we utilize bio-inspired Angle Sensitive Pixels (ASPs), custom CMOS diffractive image sensors which act similar to Gabor filter banks in the V1 layer of the human visual cortex. ASPs replace both image sensing and the first layer of a conventional CNN by directly performing optical edge filtering, saving sensing energy, data bandwidth, and CNN FLOPS to compute. Our experimental results (both on synthetic data and a hardware prototype) for a variety of vision tasks such as digit recognition, object recognition, and face identification demonstrate 97% reduction in image sensor power consumption and 90% reduction in data bandwidth from sensor to CPU, while achieving similar performance compared to traditional deep learning pipelines. Huaijin G. Chen, Suren Jayasuriya, Jiyue Yang, Judy Stephen, Sriram Sivaramakrishnan, Ashok Veeraraghavan, Alyosha C. Molnar |
CVPR | 7 |
| 2016 | Challenges and approaches to software defined duplexing radioabstractRecent advances in reconfigurable RF front end circuits, such as passive mixer first receivers have opened the door to the possibility of building radios that can be programmed to both transmit and receive across octaves of frequency while maintaining reasonable performance and extremely high levels of integration. One of the remaining challenges in software defined radio hardware is the construction of a flexible RF system capable of duplex operation. Specifically, transmitting and receiving on the same antenna across a wide band of frequencies presents a significant challenge. This paper presents some of the primary challenges that arise in this space, as well as some interesting published and potential solutions. Alyssa B. Apsel, Alyosha C. Molnar, Hazal Yüksel, Thomas Tapen, Emory Enroth, Mashrur Mohiuddin, Zachariah Boynton |
ISCAS | 2 |
| 2015 | Depth Fields: Extending Light Field Techniques to Time-of-Flight ImagingabstractA variety of techniques such as light field, structured illumination, and time-of-flight (TOF) are commonly used for depth acquisition in consumer imaging, robotics and many other applications. Unfortunately, each technique suffers from its individual limitations preventing robust depth sensing. In this paper, we explore the strengths and weaknesses of combining light field and time-of-flight imaging, particularly the feasibility of an on-chip implementation as a single hybrid depth sensor. We refer to this combination as depth field imaging. Depth fields combine light field advantages such as synthetic aperture refocusing with TOF imaging advantages such as high depth resolution and coded signal processing to resolve multipath interference. We show applications including synthesizing virtual apertures for TOF imaging, improved depth mapping through partial and scattering occluders, and single frequency TOF phase unwrapping. Utilizing space, angle, and temporal coding, depth fields can improve depth sensing in the wild and generate new insights into the dimensions of light's plenoptic function. Suren Jayasuriya, Adithya Kumar Pediredla, Sriram Sivaramakrishnan, Alyosha C. Molnar, Ashok Veeraraghavan |
3DV | 4 |
| 2014 | A switchable light field camera architecture with Angle Sensitive Pixels and dictionary-based sparse codingabstractWe propose a flexible light field camera architecture that is at the convergence of optics, sensor electronics, and applied mathematics. Through the co-design of a sensor that comprises tailored, Angle Sensitive Pixels and advanced reconstruction algorithms, we show that—contrary to light field cameras today—our system can use the same measurements captured in a single sensor image to recover either a high-resolution 2D image, a low-resolution 4D light field using fast, linear processing, or a high-resolution light field using sparsity-constrained optimization. Matthew Hirsch, Sriram Sivaramakrishnan, Suren Jayasuriya, Albert Wang 0004, Alyosha C. Molnar, Ramesh Raskar, Gordon Wetzstein |
ICCP | 5 |
| 2011 | Self-quenching, Forward-bias-reset for Single Photon Avalanche Detectors in 1.8V, 0.18µm processabstractWe present a fully integrated, Single Photon Avalanche Detector (SPAD) using only standard low-voltage (1.8V) CMOS devices in a 0.18 μm process. The system requires one high-voltage AC signal which alternately reverse biases the SPADs into avalanche breakdown and then resets with a forward bias. The proposed self-quenching circuit intrinsically suppresses after-pulse effects, improving signal to noise ratio while still permitting fine time resolution. The required high- voltage AC signal can be generated by resonant structures and can be shared across arrays of SPADs. Changhyuk Lee, Alyosha C. Molnar |
ISCAS | 2 |