This paper presents an energy-efficient continuous-time delta-sigma modulator (CTDSM) with current-reused amplifiers. The third-order single-bit modulator with finite impulse response (FIR) DAC is adopted for its superior linearity performance. In the first integrator, a two-stage hybrid compensated topology is used to achieve high gain and low noise. Meanwhile an inverter-based two-stage amplifier with a class-AB output stage is proposed for second and third integrators, achieving 2× efficiency compared to the conventional one. The proposed modulator was fabricated in 55nm CMOS process with an active area of 0.24mm2. Thanks to the current-reused amplifiers, this CTDSM consumes only 133μW from 1.2V supply. Measurement results show that the designed CTDSM achieves 92.6 dB SNDR and 94.1 dB DR over 40kHz bandwidth. The corresponding Schreier figure-of-merit is 177.3 dB.

This paper presents a behavior-level approach to improve the SQNR of incremental zoom ADCs with low hardware costs. The digital outputs of the L-th incremental zoom ΔΣ modulator are decimated using an (L+1)-th cascade-of-integrator (CoI) filter. The final quantization error is reduced through accumulating the original quantization error and then averaging. Moreover, the tonal component in the quantization error of zoom architectures is mitigated by injecting Gaussian dithering at the coarse SAR ADC input. Simulation results reveal that a dithered 2nd-order 5-bit incremental zoom ADC can achieve 114.5dB SQNR with a 3rd-order CoI decimation filter, showing a 7dB improvement over the architecture without this method. The resulting hardware overhead is only capacitors for dithering and DFFs in the digital filter, hardly raising any requirement for the analog circuit blocks.

This paper demonstrates the design of a high-resolution continuous-time (CT) incremental delta-sigma (I-$\Delta \Sigma $) analog-to-digital converter (ADC). A zero-order successive approximation register (SAR)-assisted extended counting is adopted to achieve higher resolution without affecting the thermal noise performance and conversion time. Acting like a 2-0 multi-stage noise-shaping (MASH) structure, achieving enhanced resolution and improved linearity with little power consumption is possible. Additionally, several energy-efficient techniques are adopted. Fabricated in 55-nm CMOS, the prototype occupies 0.36mm2 active area and consumes$188.6\mu $W from a 1.2-V supply. The implemented CT-IADC achieves a measured dynamic range (DR) of 96.5 dB and a signal-to-noise-and-distortion ratio (SNDR) of 95.4 dB for a maximum input of 1.9Vpp and a bandwidth of 20kHz. The measured SNDR-based Schreier figure of merit (FoM$_{\mathrm {S}}$) is 175.4 dB, the best among the reported results for CT-IADCs. It achieves a 5-dB FoMS improvement on the state-of-the-art works.

This paper describes the analysis and design of a discrete-time (DT) fully dynamic 3-0 multi-stage noise-shaping (MASH) delta-sigma ($\Delta \Sigma $) analog-to-digital converter (ADC). Through system-level analysis, error source analysis, nonlinearity analysis and modeling of the integrators, and detailed considerations for circuit implementation, the trade-offs between design parameters in the 3-0 MASH$\Delta \Sigma $ADC were evaluated. The proposed ADC is fabricated and measured in a 180 nm CMOS process, achieving a DR, peak SNDR, and SFDR of 100.2 dB, 98.5 dB, and 116.7 dB, respectively, within a 2.56 kHz bandwidth, consuming only$20.1~\mu $W. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR are 179.6 dB and 181.3 dB, respectively. The measurement results of the prototype 3-0 MASH$\Delta \Sigma $ADC closely matched the theoretical predictions. This consistency between the measurements and the theoretical analysis confirms the reliability of the design approach in achieving the expected performance.

This article presents a two-stage pipelined noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution applications. However, it asks for an accurate residue amplification to avoid severe quantization noise leakage from the frontend stage. Therefore, a charge-efficient correlated-level-shifting (CECLS) assisted residue amplifier (RA) is designed by inserting the level-shifting network (LSN) in a two-stage floating inverter amplifier (FIA). In addition to the inherited low-power merit from FIA, it boosts the equivalent open-loop gain to 92 dB while preventing bandwidth reduction and charge-sharing effects, making the amplification more accurate and faster than prior CLS-assisted amplifiers. The prototype is fabricated using 55 nm CMOS technology and occupies an active area of 0.26 mm$^{\mathbf {2}}$. The measurement results show a 96.2 dB peak-SNDR and 871 nW power consumption under a 1.2 V supply voltage with a 16 kS/s sampling rate. Compared to the recent state-of-the-art ADCs with power under$10\mu $W and SNDR exceeding 90 dB, this ADC presents the best Schreier FoM of 180.8 dB.

This work proposes a floating-inverter-amplifier (FIA) based high-precision dynamic zoom ADC for low-voltage battery-powered applications. A capacitive biasing technique is proposed to reboot the FIA under low voltages, which enables the FIA to operate under a near-threshold supply voltage. Furthermore, correlated-level-shifting (CLS) is employed to boost the DC gain of the FIA to 51 dB. Simulated in 55nm CMOS under a 0.5V supply, the zoom ADC achieves 84.3dB SNDR while only consuming 723nW at a signal bandwidth of 1kHz. This corresponds to a state-of-the-art Schreier figure-of-merit (FoM) of 175.7 dB.

Deep neural networks (DNNs) can be implemented in low-power, small-area systems using compute-in-memory (CIM). This study proposes a CIM MAC macro based on 8T SRAM and a 5-bit Successive Analog-to-Digital Data Converter (SAR ADC) readout circuit to execute low-power and highspeed calculations. This architecture has no buffers between the low-power SAR ADC and the pre-stage. The SAR ADC’s capacitors are reused throughout calculating operations. The proposed macro is implemented using 55nm technology and achieves an INT4 throughput of 23.27 GOPS per ADC and an energy efficiency of 49.85 TOPS/W with 4-bit input, 4-bit weight, and 5-bit output.

This paper presents a low-power chopper-stabilized capacitively-coupled frontend amplifier with auxiliary-path-based input impedance ( Z$_{\mathbf{in}}$) boosting. In order to achieve a high Z$_{\mathbf{in}}$, a low noise and a small chip area, techniques on both system level and circuit level are implemented. On the system level, small capacitors ( C$_{\mathbf{in}}$$=$0.5 pF, C$_{\mathbf{fb}}$$=$25 fF) are used with a biased pseudo-resistor ( R$=$2.5 G$\Omega $) fed back to an amplifier internal node. As a result, a high achievable Z$_{\mathbf{in}}$and low high-pass corner frequency are achieved. On the circuit level, an input capacitance shielded current feedback (CSCF) topology achieving effective 10 fF C$_{\mathbf{amp}}$is proposed as the core of the capacitive feedback amplifier in order not to increase the input noise. Moreover, the design space of auxiliary-path-based boosting is explored to obtain the optimal value of buffer bandwidth and auxiliary capacitor size to save power. The amplifier and its Z$_{\mathbf{in}}$boosting circuit are implemented in a standard 55 nm CMOS process and characterized experimentally. Measurement results show that the proposed amplifier provides an input noise density of 50 nV/$\surd$Hz, and an integrated noise of 0.85$\mu$V$_{\mathbf{rms}}$in 200 Hz band. The Z$_{\mathbf{in}}$is boosted to 1.92 G$\Omega $at DC and 1.02 G$\Omega $at 50 Hz with only 1.0$\mu$A in each auxiliary path buffer. The amplifier also archives 77 dB CMRR and 76 dB PSRR while consuming 20.3$\mu$W in total.

This paper presents a novel two-stage amplifier, which cascades a duty-cycled inverter-based OTA and a floating-inverter amplifier (FIA). The proposed OTA-FIA can achieve 72.0dB gain under a 1.2V supply, whose output swing is 420mV. Additionally, it exhibits intrinsic loop stability without compensation and reduces thermal noise during integration. The proposed OTA-FIA is adopted in a low distortion 1-1-1 MASH structure to obtain high resolution. Simulated in a 55 nm CMOS process, the proposed ADC can achieve an SNDR of 94.6dB with a bandwidth of 50kHz. It consumes$363.8\mu \mathrm{W}$from a 1.2V supply at a 5MS/s sampling frequency, resulting in a 176.0dB SNDR-based Schreier FoM.

A 1V 56.07dB SNDR 10MHz bandwidth digital slope ADC based on Preset Bidirectional-Shifting Technique is presented. With the proposed Preset Bidirectional-Shifting Technique, the number and conversion time are decreased impressively. Under low input frequency, the structure can achieve high resolution and high speed. Moreover, passive noise-shaping is used to implement an on-chip correction for the comparator latency. The proposed ADC is simulated in a 55nm CMOS process, achieving an SNDR of 56.07dB and consuming 941μW with a 1V supply. The simulation achieved a Schreier FoM of l56.33dB.

An ultra-low quiescent current tri-mode DC-DC buck converter is presented in this paper, which is able to handle a 100,000X load range. In pulse width modulation (PWM) and pulse frequency modulation (PFM) mode, adaptive on-time (AOT) V2control is utilized to achieve seamless mode transition and constant switching frequency in PWM mode. A deep green mode (DGM) is proposed for light load, where both the switching loss and the power of control circuitry are minimized. By reducing the comparator current, a delay-based hysteresis window adaptive to load current is generated, reducing the switching frequency and the loss. Meanwhile, the average current of zero current detector (ZCD) and AOT controller are reduced significantly by dynamic biasing. As a result, the efficiency of the converter is improved while maintaining a reasonable output ripple. The proposed converter is implemented in a$0.18\mu $m BCD technology. Experimental results show that the converter can provide a 1.6 V output from a 2.7 to 4.7V input for$1\mu $A to 100 mA load, while consuming only 490nA quiescent current. The proposed converter achieves a 92.1% peak efficiency and efficiency can be maintained above 80% in a load range of$20\mu $A to 60 mA.

Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

This paper proposes a novel probe for reliable detection of crack/defect in a conductive target. This probe is realized by combining the eddy current and capacitive sensing techniques. Lift-off is a main concern for the eddy current based defect detection systems as the output of the sensor is very sensitive to the air gap between the target and the probe. The effect is significant when the probe is kept close to the target. In the proposed probe, like in some of the conventional ones, a planar coil is used as the eddy current sensing element. The same planar coil is used as a capacitive sensing element to sense the value of the capacitance between the coil and the target. This value is a function of the air gap between the probe and the target. The measured value is fed back to a magnetic actuator on which the entire probe is fitted. The magnetic actuator uses the capacitance value information and automatically adjusts the gap between the probe and the target to a preset value. Thus, the liftoff is corrected automatically. The functionality of the new probe has been analyzed and optimized using finite element analysis before building a prototype probe. Tests conducted on the probe developed confirms the effectiveness of the probe.

In the paper, we proposed a novel framework for the sea-ice images classification, which will be very helpful for the future channel navigation in polar applications. Firstly, the three different types of sea ice are defined in the paper based on the large amounts of data inspection, such as thick ice, thin ice and water. Further, we present to use relative radiometric normalization method to solve the grayscale difference of different temporal sea-ice images, which can affect the classification accuracy of sea ice. Finally, the SAE (sparse auto-encoder) classifier is employed for different types of sea-ice classification. We designed several experiments to discuss and analyze the influence factors on the classification accuracy of sea-ice images. The experiment results indicated the validity of the proposed method and the rationality of sea ice type definition.

Arctic travel has become a significant way for commercial or scientific researches. Sea-ice is always serious threat for Arctic navigation. In this paper, a classification method of aerial images is proposed to recognize different types of sea-ice scenes, which can be further used to analyze the threat of each scene in Arctic Ocean. However, due to the diverse types and distribution of sea-ice in various scenes, the categories of sea-ice scenes are indistinct. So a grouping way is primarily introduced to define different sea-ice scenes. These scenes are grouped into six typical categories according to the distribution of sea-ice. Then a transfer learning strategy is used to fine-tune a pre-trained deep convolution neural network model. Finally, using that trained network to classify new sea ice scenes. Experimental results show that an acceptable classification accuracy can be obtained.

This paper proposes an adaptive algorithm for a predicting SAR ADC which can self-adjust the precision of its prediction. A precise and yet correct prediction reduces bit trials needed in a SAR conversion, leading to great power savings. The presented algorithm uses a 2-byte prediction-success-rate-register and a1storder digital negative feedback loop to control the prediction depth. Additionally, an offset-move-up technique is proposed to boost the prediction success rate when the previous sample is near the boundary of the predicted subrange. The boundary-crossing problem reduces energy-efficiency in other predictive SAR algorithms such as LSB-first. The proposed scheme makes aggressive predictions for low-activity biomedical signals, makes conservative predictions or no predictions for high-activity-high-amplitude signals and it automatically and smoothly transitions between the two extremes.

This paper presents a novel subtractive dithering technique used in delta-sigma modulators which improves the spectral integrity of the modulators while minimizing the tradeoffs due to the use of dither. Dithering is commonly used in delta-sigma modulators to eliminate idle tones. The proposed technique adds dither at input of the quantizer and subtracts the dither in the analog domain at input of the modulator and in the digital domain at the output of modulator. The simulation results prove that when compared to the conventional dithering technique, this new subtractive dithering technique achieves the idle tone-free result but does not have the traditional drawbacks such as increased integrator output swing and in-band noise floor degradation.