The increasing deployment of digital communications in modern society has heightened the need for security and privacy, particularly within the Internet-of-Things (IoT) domain, where cost-effective implementations remain a challenge. Post-quantum cryptography (PQC) schemes based on hard learning problems, such as learning with errors (LWEs) and learning parity with noise (LPN), have gained significant attention due to their robustness against quantum attacks. A key challenge in these cryptographic schemes is the generation of error distributions, which must maintain secrecy and adhere to specific statistical properties. Traditional approaches rely on complex two-phase sampling chains, making hardware implementations both resource-intensive and vulnerable to physical attacks. To address these challenges, inexact or approximate computing has been explored as a means of generating errors. The learning parity with physical noise (LPPN) scheme was introduced as an alternative, leveraging controllable computational inaccuracies instead of explicit error sampling. Initially demonstrated using frequency–voltage Over-Scaling techniques on a 65-nm technology, its viability on advanced semiconductor nodes remains uncertain. In this work, we implement the LPPN technique on a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology, assessing the limitations of conventional voltage–frequency Over-Scaling. Furthermore, we propose the use of back-gate voltage scaling, a unique capability of FD-SOI, to enhance error controllability. Experimental results from both simulations and on-chip measurements demonstrate that back-gate voltage scaling improves the precision of error generation, reducing the sensitivity factor of the error probability by up to four times compared to conventional methods.

The description of the physical noise source is of utmost importance for any TRNG certification. In the case of ring oscillators, Allan variance is a reliable and comprehensive tool which enables the distinction between the jitter coming from flicker noise (autocorrelated) and from thermal noise (random). In this paper, we realize measurements directly on the analog source of numerous TRNG structures: a ring oscillator. Our data, along with evidence from the literature, indicates the presence of a third noise source. The quantization noise has not been so far taken into consideration, but is unquestionably present in all TRNG reliant on jitter. Its importance is key to an accurate estimation of thermal noise contribution, which can be shadowed by it. Measurements presented in this paper show that insufficient sampling (i.e. higher quantization noise) can lead to an overestimation of jitter coming from thermal noise and therefore an overestimation of the calculated entropy. The latter is the only type of noise considered reliable in currently existing ring oscillator-based TRNG models. As a rule of thumb, three orders of magnitude between the sampling and the sampled signal are necessary in order to determine the thermal noise jitter correctly.

Integrated Circuits (ICs) have to be protected against threatening environmental radiations and malicious perturbations. A large panel of countermeasures has been developed to answer the needs of this challenging field. The Bulk Built-In Current Sensor (BBICS) is a highly reliable solution for the detection of these abnormal transient radiations that could induce a transient current in the Front-End of Line (FEoL). This paper proposes an innovative sensor based on the BBICS associated to the power-efficient emerging non-volatile memory Spin Transfer Torque Magnetic Random Access Memory (STTMRAM). The goal of this security solution is to detect both possible photoelectrical laser injections and thermal perturbations. Thus, the proposed architecture designated by Dual Detection of Heating and Photocurrent attacks (DDHP) highlights a dual detection efficiency, on the CMOS circuitry and on the Back-End of Line (BEoL) STT-MRAM technology.

Internet of Things (IoT) applications deployment relies on low-power circuits. Nowadays, on top of power consumption, security concern has become a real issue. Light-Weight Cryptography (LWC) has been developed to answer this challenge. In the lightweight cryptographic landscape, the PRESENT algorithm exhibits low power and small area features. At the same time, emergent resistive memory technologies such as Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) seem to be a strong candidate for Flash replacement with advanced design features such as hybridization with CMOS. In this context, we propose a hybrid CMOS/STT-MRAM technology for PRESENT cryptographic circuit for normally-off IoT applications. We demonstrate that the hybrid implementation is more power-efficient than the CMOS implementation when switched off for a period longer than 49.1 ms for a 180 nm CMOS core process with an area overhead of ×7. Based on this result, trends down to 28 nm node are studied and lead to outstanding performances with a power-effeciency of the hybrid version reached after 185 μs standby mode. In this scenario, an energy of 6,1 pJ is sufficient to store data in the Non-Volatile Flip-Flops (NVFFs) with a reduced area overhead of ×0.23.

The Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been identified, by the International Technology Roadmap for Semiconductors (ITRS), as one of the most promising emerging technology. Different works handled the retention and reliability of STT-MRAM. However, to the best of our knowledge, the impact of a pulsed laser beam on STT-MRAM reliability and security has not been investigated so far as proposed in this paper. Since STT-MRAM are Back-end Of Line devices, we exposed the bit cells from the front-side to a 1064 nm wavelength laser pulse. The devices are electrically characterized (switching conditions between the two logical states) before and after the laser irradiation. The main result of this study is the demonstration of a resistance switching from Anti-Parallel (AP) to Parallel (P) state after the laser irradiation. That is how data integrity was altered by this irradiation, flipping the bit stored in this memory.

The last 10 years have seen the rise of new NVM technologies as alternative solutions to Flash technology, which is facing downsizing issues. Apart from offering higher performance than the state of the art of Flash, one of their key features is lower power consumption, which makes them even more suitable for the IoT era. But one of the other main concerns regarding IoT is data security, which is yet to be evaluated for emerging NVM. Our previous work aimed at putting under test the integrity of HfO2based resistive RAM (OxRAM cells). Bit-set occurrences were found after thermal laser attacks. This present work investigates the difference in behaviour when a selector is added to the resistive element, thanks to attack on different stacks. The results obtained give interesting tracks for the design of secure OxRAM-based ICs. It also studies the kinetic role of temperature through heating experiments.