A 21.6–37.1 GHz broadband low-noise amplifier (LNA) is presented, featuring a magnetically coupled resonator (MCR) at the output stage for inherent bandwidth extension and output matching. To overcome the limitation of the MCR, which tunes only one pole, an additional coupling inductor is introduced to adjust the second pole via its coupling coefficient, enabling flexible dual-pole bandwidth extension while maintaining gain flatness. The LNA is implemented in 130-nm SiGe BiCMOS technology with a core area of$0.128~\text {mm}^{2}$. It achieves a peak gain of 21.5 dB across a 3-dB bandwidth of 21.6–37.1 GHz, with a gain ripple of 1.5 dB. The measured noise figure ranges from 1.9 to 2.6 dB, and the input 1-dB compression point ($\text {IP}_{\text {1dB}}$) remains stable between −23.5 and −21.5 dBm across the entire bandwidth. The LNA consumes 14.5 mW from a 1.2 V supply, demonstrating a compact, low-noise, and wideband design suitable for Ka-band millimeter-wave applications.

The design of a 15–28 GHz broadband low-noise amplifier (LNA) is presented, employing a magnetically coupled resonator (MCR) to achieve simultaneous bandwidth extension and output matching. To address the increased in-band ripple that occurs when enhancing bandwidth with limited on-chip inductor values, an emitter-collector feedback transformer is introduced to mitigate the MCR ripple by generating an additional pole. This approach enables bandwidth expansion while maintaining minimal gain ripple. The LNA is implemented in 90-nm SiGe BiCMOS technology, occupying a core area of$0.11~\text {mm}^{2}$. It achieves a peak gain of 19.3 dB across a 3-dB bandwidth of 15–28 GHz, with a gain ripple of 0.75 dB within the 16–26.7 GHz range. The measured noise figure (NF) ranges from 2.9 to 3.9 dB. Additionally, the input 1-dB gain compression point ($\text {IP}_{\text {1 dB}}$) remains stable between −27 and −24.5 dBm throughout the entire 3-dB gain bandwidth. The LNA consumes 9.7 mW of power from a 1.2 V supply.

A wideband high dynamic range software radio receiver for sub-6-GHz applications is proposed. The receiver combines three gain variable modules and an automatic gain control module to achieve high gain dynamic range and constant output voltage. A broadband resistive feedback LNA was designed, and two novel gain switching methods were proposed for the resistive feedback LNA, which reduced the LNA gain while optimizing the input matching performance. In addition, the receiver adopts a voltage mode mixer and uses the impedance translation property to achieve blocker-tolerant performance. In analog baseband (ABB), a fourth-order Butterworth active-RC low-pass filter (LPF) is employed for the purpose of attenuating interference. Furthermore, the receiver is furnished with an automatic gain control amplifier to uphold a consistent output voltage amplitude. A 22 nm CMOS receiver prototype occupies 1.85 mm2 and consumes 51 mW from a 1 V power supply over the 2–6 GHz operating frequency range. The receiver achieves a gain dynamic range of 9.1-91.9 dB and a noise figure (NF) of 2.4-3.4 dB. When a 0 dBm blocker with a frequency offset of 80 MHz is injected into the receiver, the NF increases to 13.2 dB. The programmable bandwidth of the LPF can be adjusted from 10 to 160 MHz. Moreover, the receiver achieved an in-band third-order input-referred intercept point (IIP3) of −9.1 dBm and an out-of-band IIP3 of −2.9 dBm respectively.

A 6–18-GHz ultrawideband vector-sum phase shifter (PS) with 6-bit digital phase control for phased-array system in SMIC 40-nm CMOS process is presented in this article. Combination of two inserted balanced buffers, elaborately optimized RC third-order I/Q signals generator, and novel complementary current source compensation technique contributes to the low rms phase and gain error. The fabricated PS exhibits a full-360° tuning range with 5.625° tuning step and good matching characteristics. The measured rms phase and gain error are,$< 1.82^{\circ }$and$_{\text {1 dB}}$) is$\ge -3.9$dBm in the frequency band of interest with a power consumption of 42 mW from a 1.2-V supply. The core chip occupies an area of 0.46 mm2.

提出一种在微波频段具有宽带、 高效率的氮化镓 (GaN)功率放大器. 该功率放大器采用0.15 μm栅长GaN-HEMT工艺, 其工作频段可以覆盖整个K频段, 即17–26.5 GHz. 为获得更好的输出功率和功率附加效率 (PAE), 根据晶体管的性能, 设计了最优前后级驱动比和最佳晶体管尺寸, 并采用宽带低损耗电路拓扑结构, 实现宽带高效率设计. 同时, 将谐波控制结构巧妙地集成到驱动级匹配电路中, 提升高频效率, 确保整个频段内获得较高功率附加效率. 该功率放大器采用三级放大拓扑结构, 在连续波条件下, 测试结果表明, 在17–26.5 GHz频带范围内饱和输出功率超过42.5 dBm, 平均PAE为30%, 在19.8 GHz时PAE达到最大, 为32.1%, 输出功率平坦度优于1.0 dB. 该芯片结构紧凑, 面积仅为4.2 mm×3.0 mm, 可广泛应用于收发组件、 无线通信、 电子测量仪器等领域.

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit.

This article describes a wideband low-noise frequency synthesizer implemented in 0.13-μm SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range while reducing the phase noise, a fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted in the proposed frequency synthesizer. A ring-oscillator-based injection locked frequency divider is utilized as the wideband divideby-2 prescaler, and its bandwidth is optimized based on a new injection-locked behavior model. This fabricated frequency synthesizer can be locked in a range from 23 to 36.8 GHz (46.2%) by a 100-MHz step. It achieves a phase noise of -94.7 dBc/Hz at the 1-MHz offset and an output power of -3.5 dBm measured at 36.8 GHz. The chip consumes 360.6 mW from 3.3 and 1.8 V supplies and has an area of 2.7 × 3.1 mm2.

The IEEE 802.11ah complements the other standards to provide support for machine-type communications (MTC) in local area network using a different spectrum from the highly congested WLAN operating at 2.4GHz/5GHz ISM bands. In order to satisfy massive station communications, the paper presents traffic indication map (TIM) compressed scheme for the Internet of Things and Smart Grid based on IEEE 802.11ah. The simulation results are discussed by evaluating the impact of the TIM compression on the system performance and cost. Results indicate that the proposed scheme has an acceptable cost and can support massive communications with higher performance enhancement. The proposed compressed TIM indication length can efficiently save the TIM bit map space and simultaneously be superior to the traditional structure.

We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator (LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency (IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power (LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain (VCG) of 9.8 dB, a double sideband noise figure (DSB-NF) of 11.6 dB, and a linearity in terms of input 1 dB compression point (P in,1dB) of −13 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 mW.

A 37 GHz wide-band programmable divide-by- N frequency divider (FD) composed of a divide-by-2 divider (acting as the first stage) and a divider with a division ratio range of 273–330 (acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider (with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic (DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as −20 dBm at 32 GHz and the phase noise at 37 GHz is less than −130 dBc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 mW at a supply voltage of 1.2 V and occupies an area of only 730 μm ×475 μm.

We present a 31–45.5 GHz injection-locked frequency divider (ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 dBm. The power consumption is 2.88 mW under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.

A Ka-band sub-harmonically pumped resistive mixer (SHPRM) was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance (balun) with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation (LO) signal from single to differential mode. The results showed that the SHPRM achieves the conversion gain of −15–−12.5 dB at fixed f IF=0.5 GHz with 8 dBm LO input power for the radio frequency (RF) bandwidth of 28–35 GHz. The in-band LO-intermediate freqency (IF), RF-IF, and LO-RF isolations are better than 31, 34, and 36 dB, respectively. Besides, the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB, respectively. The measured input referred P1dB and 3rd-order inter-modulation intercept point (IIP3) are 0.5 and 10.5 dBm, respectively. The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm2 including pads.