Two new general designs for totally self-checking (TSC) comparators with an arbitrary number of input vectors are presented. The multipattern comparator combines modified TSC 2-input comparators and a TSC two-rail checker that requires only four patterns for self-testing. The counter-driven comparator adds circuitry to generate an exhaustive set of test patterns. The designs are compared on the basis of input limitations, circuit complexity, and gate delays. It is shown that TSC comparators cannot exist under two sets of conditions associated with 1-bit input vectors and two-level circuit realizations.

Quantitative measures of self-checking power are defined for evaluation, comparison, and design of self-checking circuits. The self-testing and fault-secure properties have the corresponding quantitative measures testing input fraction (TIF), and secure input fraction (SIF). Averaging these measures over the fault set yields basic figures of merit. These simple averages can conceal faults with low values of TIF or SIF. Improved figures of merit, based on geometric means, are defined to provide greater sensitivity to low TIF or SIF. As a demonstration, self-checking linear feedback shift registers (LFR's) based on duplication and serial parity prediction are evaluated.

The use of watchdog processors in the implementation of Structural Integrity Checking (SIC) is described. A model for ideal SIC is given in terms of formal languages and automata. Techniques for use in implementing SIC are presented. The modification of a Pascal compiler into an SIC Pascal preprocessor is summarized.