Increasing complexity of modern designs and high costs of test equipment are putting more and more emphasis on test application times. This paper presents a classification of methods for reducing the test time of a device by exploiting parallelism in Macro Test. Techniques and considerations are given for different methods of parallel testing. It is shown that without design modifications significant reductions in test time can be reached. To obtain a further test time reduction, analysis of resource sharing conflicts is done in order to be able to decide which design modifications can best be made. As a result, a trade-off between test time and additional testability hardware can be made. Results of one of the methods of parallel testing are given for two industrial devices. Test time reductions of up to 40-50% compared to sequential approaches have been reached without making any design modifications.>

Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses.>

The authors present a testability strategy for complex VLSI devices which is implemented in the PIRAMID Digital Signal Processor Silicon Compiler. The macrotest methodology supports built-in self-test, scan test, bus test control, restricted partial scan and test control logic at various levels in the design hierarchy. A set of testability design rules is developed and implemented automatically in the design. The design hierarchy is closely followed, resulting in a hierarchical set of testable macros. The complete process from design to final test program is guided by software tools. As an example, the synthesis of a large industrial circuit is presented for comparing the proposed approach with the traditional approaches. The additional overhead due to testability is within reasonable limits (roughly 8%), and the software run time figures show that it is possible to generate a test program with an excellent fault coverage within a very short period of time.>

A fault model for SRAMs (static random-access memories) is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) plus a data retention test are proposed that cover 100% of the faults under the fault model. The 13N test algorithm is generally applicable while the 9N algorithm can only be used in SRAMs with combinational R/W logic. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms is verified by a large number of actual wafer tests and device failure analysis.>

A self-test machine for static random access memories (SRAMs) has been developed. It is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds. The test algorithm implemented has excellent fault-detection capabilities and is extremely regular and symmetric, which results in a minimum of hardware overhead and performance loss. Self-test reduces the possibilities for diagnostic tests. A form of scan test remains necessary in spite of a self-test implementation. This self-test design offers full scan test facilities of both the SRAM and the self-test logic itself. This version of the SRAM self-test is currently being implemented in a number of digital signal processing chips and will, after a final evaluation, be used for a broad scope of designs.>

A method for designing easily testable PLA's with low overhead is presented. The method is based on a reduction of product lines and the addition of a small number of inputs. The required additional hardware is calculated using a statistical cooling algorithm. The presented design-for-testability method guarantees a 100 percent fault coverage with respect to multiple stuck-at faults and multiple missing/extra crosspoint faults.